# X410_FPGA

This documentation provides a description of the different register spaces available for the USRP X4xx Open-Source FPGA target implementation, accessible through the embedded ARM A53 processor in the RFSoC chip, and other UHD hosts.

The top is defined in HDL source file x410_rfdc_regs.v, x4xx.v.

## P5 Content

### Register map supplied for open-source projects

"All content provided is Copyright 2023 National Instruments Corporation. For information on NI trademark guidelines, please see http://www.ni.com/legal/trademarks/. For the NI Patent Notice, please see http://www.ni.com/legal/patents/."

## ports

This section lists all common Processing System ports through which the register maps in this project are accessed. Each input port to the fabric will point to a regmap.

### Port ARM_M_AXI_HPM0 (input)

Target Regmap = AXI_HPM0_REGMAP

This is the main AXI4-Lite master interface that the PS exposes to the kernel to interact with the FPGA fabric. There are multiple endpoints connected to this interface.

This port is defined in HDL source file x410_rfdc_regs.v.

### Port ARM_S_AXI_HPC0 (output)

Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW

This is one of the two cache-coherent AXI slave ports available to communicate from the fabric (master) to the PS (slave).

This port is defined in HDL source file x410_rfdc_regs.v.

### Port ARM_S_AXI_HPC1 (output)

Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW

This is one of the two cache-coherent AXI slave ports available to communicate from the fabric (master) to the PS (slave).

This port is defined in HDL source file x410_rfdc_regs.v.

### Port ARM_SPI1_CS3 (input)

Target Regmap = MB_CPLD_PS_REGMAP

This is the SPI1 interface (see Zynq UltraScale+ Devices Register Reference) of the PS. With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.
The request format on SPI is defined as.
Write request:

- 1'b1 = write
- 15 bit address
- 32 bit data (MOSI)
- 8 bit processing gap
- 5 bit padding
- 1 bit ack
- 2 bit status

Read request:

- 1'b0 = read
- 15 bit address
- 8 bit processing gap
- 32 bit data (MISO)
- 5 bit padding
- 1 bit ack
- 2 bit status

This port is defined in HDL source file x410_rfdc_regs.v.

# AXI_HPM0_REGMAP

This is the map for the register space that the Processing System's M_AXI_HPM0_FPD port (AXI4 master interface) has access to. This port has a 40-bit address bus.

## COMMON

### Offset 0x80000000: RPU Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
RPU
offset=0x80000000
size=0x10000 (64 Kbytes)
Total Offset =
0x80000000

This window is defined in HDL source file common_regs.v.

Space reserved for RPU access

### Offset 0x1000000000: JTAG_ENGINE Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
JTAG_ENGINE
offset=0x1000000000
size=0x1000 (4 Kbytes)
Total Offset =
0x1000000000

This window is defined in HDL source file common_regs.v.

Register space for the JTAG engine for MB CPLD programming.

### Offset 0x100003F000: RESERVED Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
RESERVED
offset=0x100003F000
size=0x1000 (4 Kbytes)
Total Offset =
0x100003F000

This window is defined in HDL source file common_regs.v.

Register space reserved for future use.

### Offset 0x1000080000: MPM_ENDPOINT Window (R|W)

Target regmap = PL_CPLD_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
MPM_ENDPOINT
offset=0x1000080000
size=0x20000 (128 Kbytes)
Total Offset =
0x1000080000

This window is defined in HDL source file common_regs.v.

MPM endpoint fro MB/DB communication.

### Offset 0x10000A0000: CORE_REGS Window (R|W)

Target regmap = CORE_REGS_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
CORE_REGS
offset=0x10000A0000
size=0x4000 (16 Kbytes)
Total Offset =
0x10000A0000

This window is defined in HDL source file common_regs.v.

Register space reserved for mboard-regs (Core).

### Offset 0x10000A4000: INT_ETH_DMA Window (R|W)

Target regmap = ETH_DMA_CTRL_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
INT_ETH_DMA
offset=0x10000A4000
size=0x6000 (24 Kbytes)
Total Offset =
0x10000A4000

This window is defined in HDL source file common_regs.v.

AXI DMA engine for internal Ethernet interface.

### Offset 0x10000AA000: INT_ETH_REGS Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
INT_ETH_REGS
offset=0x10000AA000
size=0x2000 (8 Kbytes)
Total Offset =
0x10000AA000

This window is defined in HDL source file common_regs.v.

Misc. registers for internal Ethernet.

### Offset 0x1000100000: RFDC Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
RFDC
offset=0x1000100000
size=0x40000 (256 Kbytes)
Total Offset =
0x1000100000

This window is defined in HDL source file common_regs.v.

Register space occupied by the Xilinx RFDC IP block.

### Offset 0x1000140000: RFDC_REGS Window (R|W)

Target regmap = RFDC_REGS_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
RFDC_REGS
offset=0x1000140000
size=0x20000 (128 Kbytes)
Total Offset =
0x1000140000

This window is defined in HDL source file common_regs.v.

Register space for RFDC control/status registers.

## UHD_ONLY

- 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
- 0_1 indicates QSFP0 - Lane1
- 0_2 indicates QSFP0 - Lane2
- 0_3 indicates QSFP0 - Lane3
- 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
- 1_1 indicates QSFP1 - Lane1
- 1_2 indicates QSFP1 - Lane2
- 1_3 indicates QSFP1 - Lane3

### Offset 0x1200000000: QSFP_0_0 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_0_0
offset=0x1200000000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200000000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x1200010000: QSFP_0_1 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_0_1
offset=0x1200010000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200010000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x1200020000: QSFP_0_2 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_0_2
offset=0x1200020000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200020000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x1200030000: QSFP_0_3 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_0_3
offset=0x1200030000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200030000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x1200040000: QSFP_1_0 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_1_0
offset=0x1200040000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200040000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x1200050000: QSFP_1_1 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_1_1
offset=0x1200050000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200050000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x1200060000: QSFP_1_2 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_1_2
offset=0x1200060000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200060000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x1200070000: QSFP_1_3 Window (R|W)

Target regmap = QSFP_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
QSFP_1_3
offset=0x1200070000
size=0x10000 (64 Kbytes)
Total Offset =
0x1200070000

This window is defined in HDL source file uhd_regs.v.

# MB_CPLD_PS_REGMAP

This register map is available using the PS CPLD SPI interface.

## MB_CPLD_PS_WINDOWS

### Offset 0x0000: PS_REGISTERS Window (R|W)

Target regmap = PS_CPLD_BASE_REGMAP

(show extended info)

Port ARM_SPI1_CS3
PS_REGISTERS
offset=0x0000
size=0x40 (64 bytes)
Total Offset =
0x000000

This window is defined in HDL source file mb_cpld.v.

### Offset 0x0040: RECONFIG Window (R|W)

Target regmap = RECONFIG_REGMAP

(show extended info)

Port ARM_SPI1_CS3
RECONFIG
offset=0x0040
size=0x20 (32 bytes)
Total Offset =
0x000040

This window is defined in HDL source file mb_cpld.v.

### Offset 0x0060: POWER_REGISTERS Window (R|W)

Target regmap = PS_POWER_REGMAP

(show extended info)

Port ARM_SPI1_CS3
POWER_REGISTERS
offset=0x0060
size=0x20 (32 bytes)
Total Offset =
0x000060

This window is defined in HDL source file mb_cpld.v.

## PS_SPI_ENDPOINTS

### SPI_ENDPOINT Enumeration

Value | Name
0 | PS_CS_MB_CPLD
1 | PS_CS_LMK32
2 | PS_CS_TPM
3 | PS_CS_PHASE_DAC
4 | PS_CS_DB0_CAL_EEPROM
5 | PS_CS_DB1_CAL_EEPROM
6 | PS_CS_CLK_AUX_DB
7 | PS_CS_IDLE

This enumerated type is defined in HDL source file mb_cpld.v.

# CMAC_REGMAP

## XILINX_CMAC_REGISTERS

100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.

- http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf

# CONSTANTS_REGMAP

## CONSTANTS_GROUP

Basic registers containing version and capabilities information.

### CONSTANTS_ENUM Enumeration

This enumeration is used to create the constants held in the basic registers.

Value | Name
Dec | Hex
173157671 | 0x0A522D27 | PS_CPLD_SIGNATURE
538059028 | 0x20122114 | OLDEST_CPLD_REVISION
570950676 | 0x22080414 | CPLD_REVISION
1071406151 | 0x3FDC5C47 | PL_CPLD_SIGNATURE

This enumerated type is defined in HDL source file mb_cpld.v.

# CORE_REGS_REGMAP

This is the map for the registers that the CORE_REGS window has access to from the ARM_AXI_HPM0_FPD port. The registers contained here conform the mboard-regs node that MPM uses to manage general FPGA control/status calls, such as versioning, timekeeper, GPIO, etc. The following diagram shows how the communication bus interacts with the modules in CORE_REGS.

## CORE_REGS

### Offset 0x0000: GLOBAL_REGS Window (R|W)

Target regmap = GLOBAL_REGS_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
GLOBAL_REGS
offset=0x0000
size=0xC00 (3 Kbytes)
Total Offset =
0x10000A0000

This window is defined in HDL source file x4xx_core_common.v.

Window to access global registers in the FPGA.

### Offset 0x0C00: VERSIONING_REGS Window (R|W)

Target regmap = VERSIONING_REGS_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
VERSIONING_REGS
offset=0x0C00
size=0x400 (1 Kbyte)
Total Offset =
0x10000A0C00

This window is defined in HDL source file x4xx_core_common.v.

Window to access versioning registers in the FPGA.

### Offset 0x1000: TIMEKEEPER_A Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
TIMEKEEPER_A
offset=0x1000
size=0x20 (32 bytes)
Total Offset =
0x10000A1000

This window is defined in HDL source file x4xx_core_common.v.

Window to access the timekeeper register map.

### Offset 0x1100: TIMEKEEPER_B Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
TIMEKEEPER_B
offset=0x1100
size=0x20 (32 bytes)
Total Offset =
0x10000A1100

This window is defined in HDL source file x4xx_core_common.v.

Window to access the timekeeper register map.

### Offset 0x2000: DIO Window (R|W)

Target regmap = DIO_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
DIO
offset=0x2000
size=0x40 (64 bytes)
Total Offset =
0x10000A2000

This window is defined in HDL source file x4xx_core_common.v.

Window to access the DIO register map.

# CPLD_INTERFACE_REGMAP

## CPLD_INTERFACE_REGS

Basic registers containing version and capabilities information.

### Offset 0x0000: SIGNATURE_REGISTER Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|BASE
0x000000
SIGNATURE_REGISTER
offset=0x0000
Total Offset =
0x1000080000

Initial Value not specified

This register is defined in HDL source file cpld_interface_regs.v.

Contains the product's signature.

Bits | Name
31..0 | PRODUCT_SIGNATURE fixed value 0xCB1D1FAC

### Offset 0x000C: SCRATCH_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|BASE
0x000000
SCRATCH_REGISTER
offset=0x000C
Total Offset =
0x100008000C

Initial Value not specified

This register is defined in HDL source file cpld_interface_regs.v.

Read/write register for general software use.

## CPLD_SPI_CONTROL_REGS

Registers to control the SPI clock frequency of the CPLD interfaces. The resulting clock frequency is calculated by f PRC 2(divider+1).
Note that the PLL Reference Clock (PRC) is depending on the RF clocks.

### Offset 0x0020: MOTHERBOARD_CPLD_DIVIDER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|BASE
0x000000
MOTHERBOARD_CPLD_DIVIDER
offset=0x0020
Total Offset =
0x1000080020

Initial Value = 0x00000002

This register is defined in HDL source file cpld_interface_regs.v.

Clock divider used for SPI transactions targeting the MB CPLD.
Minimum required value is 2.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..0 | MB_DIVIDER (initialvalue=2) Divider value

### Offset 0x0024: DAUGHTERBOARD_CPLD_DIVIDER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|BASE
0x000000
DAUGHTERBOARD_CPLD_DIVIDER
offset=0x0024
Total Offset =
0x1000080024

Initial Value = 0x00000005

This register is defined in HDL source file cpld_interface_regs.v.

Clock divider used for SPI transactions targeting any of the DB CPLDs.
Minimum required value is 5.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..0 | DB_DIVIDER (initialvalue=5) Divider value

## IPASS_REGS

### Offset 0x0010: IPASS_CONTROL Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|BASE
0x000000
IPASS_CONTROL
offset=0x0010
Total Offset =
0x1000080010

Initial Value not specified

This register is defined in HDL source file cpld_interface_regs.v.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..1 | Reserved
0 | IPASS_ENABLE_TRANSFER If 1 enables the forwarding of iPass cable present signal to MB CPLD using ctrlport requests. On change from 0 to 1 the current status is transferred to the MB CPLD via SPI ctrlport request initially.

# DIG_IFC_REGMAP

## SPI_OVER_GPIO_REGS

### Offset 0x0000: SPI_SLAVE_CONFIG(3:0) Register Array (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
0x002000
SPI_SLAVE_CONFIG
offset=0x0000 + i*4
Cannot determine accessibility through this path
Total Offset =
0x00E000 + i*4

Initial Values

default | => | 0x00000000

This register is defined in HDL source file x4xx_gpio_spi.v.
It uses RegType SPI_SETUP which is defined in HDL source file x4xx_gpio_spi.v.

Controls SPI Transaction
Set of configuration registers for the supported slaves.

Bits | Name
31..28 | Reserved
27 | MOSI_EDGE (initialvalue=0) Controls the edge in which the MOSI line is updated. 0 = falling edge of SCLK. 1 = rising edge of SCLK.
26 | MISO_EDGE (initialvalue=0) Controls the edge in which the MISO line is latched. 0 = falling edge of SCLK. 1 = rising edge of SCLK.
25..20 | SPI_LENGTH (initialvalue=0) Indicates the length of SPI transactions to this slave.
19..15 | SLAVE_CS (initialvalue=0) Indicates which GPIO line to use for the CS signal. 0-11 : Port A GPIO 16-27: Port B GPIO
14..10 | SLAVE_MISO (initialvalue=0) Indicates which GPIO line to use for the MISO signal. 0-11 : Port A GPIO 16-27: Port B GPIO
9..5 | SLAVE_MOSI (initialvalue=0) Indicates which GPIO line to use for the MOSI signal. 0-11 : Port A GPIO 16-27: Port B GPIO
4..0 | SLAVE_CLK (initialvalue=0) Indicates which GPIO line to use for the SCLK signal. 0-11 : Port A GPIO 16-27: Port B GPIO

### Offset 0x0010: SPI_TRANSACTION_CONFIG Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
0x002000
SPI_TRANSACTION_CONFIG
offset=0x0010
Total Offset =
0x00E010

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_spi.v.

Controls clock rate and target for subsequent SPI transactions.

Bits | Name
31..24 | Reserved
23..18 | Reserved
17..16 | SPI_SLAVE_SELECT (initialvalue=0)
15..0 | SPI_CLK_DIV (initialvalue=0) Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)]

### Offset 0x0014: SPI_TRANSACTION_GO Register (W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
0x002000
SPI_TRANSACTION_GO
offset=0x0014
Total Offset =
0x00E014

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_spi.v.

Starts a SPI transaction

Bits | Name
31..0w | SPI_DATA (initialvalue=0) Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits, it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.

### Offset 0x0018: SPI_STATUS Register (R)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
0x002000
SPI_STATUS
offset=0x0018
Total Offset =
0x00E018

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_spi.v.

Contains the status of the SPI engine.

Bits | Name
31..25 | Reserved
24 | SPI_READY (initialvalue=0) Indicates the SPI engine is ready to start a new SPI transaction.
23..0 | SPI_RESPONSE (initialvalue=0) Records the response of the last completed SPI transaction.

### Offset 0x001C: CONTROLLER_INFO Register (R)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
0x002000
CONTROLLER_INFO
offset=0x001C
Total Offset =
0x00E01C

Initial Value not specified

This register is defined in HDL source file x4xx_gpio_spi.v.

Contains information pertaining this SPI controller block.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..4 | Reserved
3..0 | SLAVE_COUNT Indicates the number SPI slaves configurable by the controller.

# DIO_REGMAP

## DIO_REGS

Registers to control the GPIO buffer direction on the FPGA connected to the DIO board. Further registers enable different sources to control and read the GPIO lines as master. The following diagram shows how source selection multiplexers are arranged, as well as an indicator for the register that control them. Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.

### Offset 0x0000: DIO_MASTER_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
DIO_MASTER_REGISTER
offset=0x0000
Total Offset =
0x10000A2000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D000

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Sets whether the DIO signal line is driven by this register interface or the user application.
0 = user application is master, 1 = output of SW_DIO_CONTROL is master

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x0004: DIO_DIRECTION_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
DIO_DIRECTION_REGISTER
offset=0x0004
Total Offset =
0x10000A2004
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D004

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Set the direction of FPGA buffer connected to DIO ports on the DIO board.
Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x0008: DIO_INPUT_REGISTER Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
DIO_INPUT_REGISTER
offset=0x0008
Total Offset =
0x10000A2008
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D008

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Status of each bit at the FPGA input.

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x000C: DIO_OUTPUT_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
DIO_OUTPUT_REGISTER
offset=0x000C
Total Offset =
0x10000A200C
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D00C

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Controls the values on each DIO signal line in case the line master is set to PS in DIO_MASTER_REGISTER.

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x0010: DIO_SOURCE_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
DIO_SOURCE_REGISTER
offset=0x0010
Total Offset =
0x10000A2010
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D010

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER or the radio blocks. 0 = DIO_MASTER_REGISTER, 1 = Radio block output(DIO_OVERRIDE)

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x0014: RADIO_SOURCE_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
RADIO_SOURCE_REGISTER
offset=0x0014
Total Offset =
0x10000A2014
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D014

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Controls which radio block to use the ATR state from to determine the state of the DIO lines. 0 = Radio#0 1 = Radio#1

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x0018: INTERFACE_DIO_SELECT Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
INTERFACE_DIO_SELECT
offset=0x0018
Total Offset =
0x10000A2018
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D018

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Controls which of the two available digital interfaces controls the DIO lines. 0 = Digital interface from Radio#0, 1 = Digital Interface from Radio#1.

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x001C: DIO_OVERRIDE Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
DIO_OVERRIDE
offset=0x001C
Total Offset =
0x10000A201C
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D01C

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Controls whether the radio input to the DIO_SOURCE_REGISTER mux connects to the ATR control or a Digital interface block. The output of the mux controlled by this bit goes to DIO_SOURCE_REGISTER. 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive Digital interface block(Output of INTERFACE_DIO_SELECT).

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

### Offset 0x0020: SW_DIO_CONTROL Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|DIO
0x002000
SW_DIO_CONTROL
offset=0x0020
Total Offset =
0x10000A2020
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
0x001000
Total Offset =
0x00D020

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

Holds a single bit setting for DIO lines in both ports. One bit per pin.
Controls which source is forwarded to the DIO_MASTER_REGISTER mux. This configuration is applied independently for each DIO line. 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.

Bits | Name
31..28 | Reserved
27..16 | DIO_PORT_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_PORT_A (initialvalue=0)

# DMA_REGMAP

## XILINX_DMA_REGISTERS

Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11

- https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

# ETH_DMA_CTRL_REGMAP

This is the map that the nixge driver uses in Ethernet DMA to move data between the Processing System's architecture and the fabric. This map is a combination of two main components: a Xilix AXI DMA engine and some registers for MAC/PHY control.

## ETH_DMA_CTRL

### Offset 0x0000: AXI_DMA_CTRL Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|INT_ETH_DMA
0x10000A4000
AXI_DMA_CTRL
offset=0x0000
size=0x4000 (16 Kbytes)
Total Offset =
0x10000A4000

This window is defined in HDL source file common_regs.v.

Refer to Xilinx' AXI DMA v7.1 IP product guide for further information on this register map: https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

### Offset 0x4000: ETH_IO_CTRL Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|INT_ETH_DMA
0x10000A4000
ETH_IO_CTRL
offset=0x4000
size=0x2000 (8 Kbytes)
Total Offset =
0x10000A8000

This window is defined in HDL source file common_regs.v.

MAC/PHY control for the Ethernet interface.

# GLOBAL_REGS_REGMAP

## GLOBAL_REGS

### Offset 0x0000: COMPAT_NUM_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
COMPAT_NUM_REG
offset=0x0000
Total Offset =
0x10000A0000

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Revision number

Bits | Name
31..16 | COMPAT_MAJOR
15..0 | COMPAT_MINOR

### Offset 0x0004: DATESTAMP_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
DATESTAMP_REG
offset=0x0004
Total Offset =
0x10000A0004

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Build datestamp (32-bit)

Bits | Name
31..27 | DAY
26..23 | MONTH
22..17 | YEAR This is the year number after 2000 (e.g. 2019 = d19).
16..12 | HOUR
11..6 | MINUTES
5..0 | SECONDS

### Offset 0x0008: GIT_HASH_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
GIT_HASH_REG
offset=0x0008
Total Offset =
0x10000A0008

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Git hash of source commit.

### Offset 0x000C: SCRATCH_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
SCRATCH_REG
offset=0x000C
Total Offset =
0x10000A000C

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Scratch register for testing.

### Offset 0x0010: DEVICE_ID_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
DEVICE_ID_REG
offset=0x0010
Total Offset =
0x10000A0010

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Register that contains the motherboard's device ID.

Bits | Name
31 | PCIE_PRESENT_BIT Set to 1 if PCI-Express core is present in FPGA design.
30..24 | Reserved
23..16 | Reserved
15..0 | DEVICE_ID

### Offset 0x0014: RFNOC_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
RFNOC_INFO_REG
offset=0x0014
Total Offset =
0x10000A0014

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Register that provides information on the RFNoC protocol.

Bits | Name
31..16 | CHDR_WIDTH
15..8 | RFNOC_PROTO_MAJOR
7..0 | RFNOC_PROTO_MINOR

### Offset 0x0018: CLOCK_CTRL_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
CLOCK_CTRL_REG
offset=0x0018
Total Offset =
0x10000A0018

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_global_regs.v.

Control register for clocking resources.

Bits | Name
31..24 | PPS_BRC_DELAY Number of base reference clock cycles from appearance of the PPS rising edge to the occurrence of the aligned edge of base reference clock and PLL reference clock at the sample PLL output. This number is the sum of the actual value based on PLL_SYNC_DELAY (also accumulate the fixed amount of clock cycles) and if any the number of cycles the SPLL requires from issuing of the SYNC signal to the aligned edge (with LMK04832 = 0). The number written to this register has to be reduced by 1 due to HDL implementation.
23..16 | PLL_SYNC_DELAY Due to the HDL implementation the rising edge of the SYNC signal for the LMK04832 is generated 2 clock cycles after the PPS rising edge. This delay can be further increased by setting this delay value (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles). In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles higher than the slave delay value to align the LMK sync edges in time.
15..10 | Reserved
9r | PLL_SYNC_DONE Indicates the success of the PLL reset started by PLL_SYNC_TRIGGER. Reset on deassertion of PLL_SYNC_TRIGGER.
8w | PLL_SYNC_TRIGGER Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge. There is no self reset on this trigger. Keep this trigger asserted until PLL_SYNC_DONE is asserted.
7..6 | Reserved
5..4 | TRIGGER_IO_SELECT (initialvalue=TRIG_IO_INPUT) IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore and/or re-sync after enabling this port, since the output-enable is basically asynchronous to the actual TRIG_IO driver. The values for this bitfield are in the TRIG_IO_ENUM table. (show here)
Value | Name
0 | TRIG_IO_INPUT
1 | TRIG_IO_PPS_OUTPUT
This enumerated type is defined in HDL source file x4xx_global_regs.v.
3r | REFCLK_LOCKED RESERVED. This bit is not implemented on X4xx and reads as 0.
2 | REF_SELECT RESERVED. This bit is not implemented on X4xx and reads as 0.
1..0 | PPS_SELECT (initialvalue=PPS_INT_25MHZ) Select the source of the PPS signal. For the internal generation the value depending on the base reference clock has to be chosen. The external reference is taken from the PPS_IN pin and is independent of the base reference clock. The values for this bitfield are in the PPS_ENUM table. (show here)
Value | Name
0 | PPS_INT_25MHZ
1 | PPS_INT_10MHZ
2 | PPS_EXT
This enumerated type is defined in HDL source file x4xx_global_regs.v.

### Offset 0x001C: PPS_CTRL_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
PPS_CTRL_REG
offset=0x001C
Total Offset =
0x10000A001C

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Control registers for PPS generation.

Bits | Name
31 | PPS_RC_ENABLED Enables the PPS signal in radio clock domain. Please make sure that the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and PRC_RC1_DIVIDER are set before enabling this bit. It is recommended to disable the PPS for changes on the other values. Use a wait time of at least 1 second before changing this value to ensure the values are stable for the next PPS edge.
30 | Reserved
29..28 | PRC_RC0_DIVIDER Clock multiplier used to generate radio clock 0 from PLL reference clock. The value written to the register has to be reduced by 2 due to HDL implementation.
27..26 | PRC_RC1_DIVIDER Clock multiplier used to generate radio clock 1 from PLL reference clock. The value written to the register has to be reduced by 2 due to HDL implementation.
25..0 | PPS_PRC_DELAY The number of PLL reference clock cycles from one aligned edge to the desired aligned edge to issue the PPS in radio clock domain. This delay is configurable to any aligned edge within a maximum delay of 1 second (period of PPS). The value written to the register has to be reduced by 4 due to HDL implementation.

### Offset 0x0020: CHDR_CLK_RATE_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
CHDR_CLK_RATE_REG
offset=0x0020
Total Offset =
0x10000A0020

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns the RFNoC bus clock rate (CHDR).

Bits | Name
31..0 | CHDR_CLK

### Offset 0x0024: CHDR_CLK_COUNT_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
CHDR_CLK_COUNT_REG
offset=0x0024
Total Offset =
0x10000A0024

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns the count value of a free-running counter driven by the RFNoC CHDR bus clock.

### Offset 0x0028: BUILD_SEED_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
BUILD_SEED_REG
offset=0x0028
Total Offset =
0x10000A0028

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Build seed used for this compilation. Making this value readable ensures that compilation results are affected by the value in this register.

### Offset 0x0038: GPS_CTRL_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
GPS_CTRL_REG
offset=0x0038
Total Offset =
0x10000A0038

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

RESERVED. This register is not implemented on X4xx. GPS is connected to the PS via a UART.

### Offset 0x003C: GPS_STATUS_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
GPS_STATUS_REG
offset=0x003C
Total Offset =
0x10000A003C

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

RESERVED. This register is not implemented on X4xx. GPS is connected to the PS via a UART.

### Offset 0x0040: DBOARD_CTRL_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
DBOARD_CTRL_REG
offset=0x0040
Total Offset =
0x10000A0040

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

RESERVED. This register is not implemented on X4xx.

### Offset 0x0044: DBOARD_STATUS_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
DBOARD_STATUS_REG
offset=0x0044
Total Offset =
0x10000A0044

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

RESERVED. This register is not implemented on X4xx.

### Offset 0x0048: NUM_TIMEKEEPERS_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
NUM_TIMEKEEPERS_REG
offset=0x0048
Total Offset =
0x10000A0048

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Register that specifies the number of timekeepers in the core.

### Offset 0x004C: SERIAL_NUM_LOW_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
SERIAL_NUM_LOW_REG
offset=0x004C
Total Offset =
0x10000A004C

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Least significant bytes of 8 byte serial number

### Offset 0x0050: SERIAL_NUM_HIGH_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
SERIAL_NUM_HIGH_REG
offset=0x0050
Total Offset =
0x10000A0050

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Most significant bytes of 8 byte serial number

### Offset 0x0054: MFG_TEST_CTRL_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
MFG_TEST_CTRL_REG
offset=0x0054
Total Offset =
0x10000A0054

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Control register for mfg_test functions.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..2 | Reserved
1 | MFG_TEST_EN_FABRIC_CLK When enabled, routes data_clk to FPGA_REF_CLK output port. When disabled, the FPGA_REF_CLK output is driven to 0.
0 | MFG_TEST_EN_GTY_RCV_CLK When enabled, routes data_clk to GTY_RCV_CLK output port. When disabled, the GTY_RCV_CLK output is driven to 0.

### Offset 0x0058: MFG_TEST_STATUS_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
MFG_TEST_STATUS_REG
offset=0x0058
Total Offset =
0x10000A0058

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Status register for mfg_test functions.

Bits | Name
31..26 | Reserved
25..0 | MFG_TEST_FPGA_AUX_REF_FREQ Report the time between rising edges on the FPGA_REF_CLK input port in 40 MHz Clock ticks. If the count extends to 1.2 seconds without an edge, the value reported is set to zero.

### Offset 0x0060: QSFP_PORT_0_0_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_0_0_INFO_REG
offset=0x0060
Total Offset =
0x10000A0060

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP0 Lane0.

### Offset 0x0064: QSFP_PORT_0_1_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_0_1_INFO_REG
offset=0x0064
Total Offset =
0x10000A0064

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP0 Lane1.

### Offset 0x0068: QSFP_PORT_0_2_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_0_2_INFO_REG
offset=0x0068
Total Offset =
0x10000A0068

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP0 Lane2.

### Offset 0x006C: QSFP_PORT_0_3_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_0_3_INFO_REG
offset=0x006C
Total Offset =
0x10000A006C

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP0 Lane3.

### Offset 0x0070: QSFP_PORT_1_0_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_1_0_INFO_REG
offset=0x0070
Total Offset =
0x10000A0070

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP1 Lane0.

### Offset 0x0074: QSFP_PORT_1_1_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_1_1_INFO_REG
offset=0x0074
Total Offset =
0x10000A0074

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP1 Lane1.

### Offset 0x0078: QSFP_PORT_1_2_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_1_2_INFO_REG
offset=0x0078
Total Offset =
0x10000A0078

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP1 Lane2.

### Offset 0x007C: QSFP_PORT_1_3_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|GLOBAL_REGS
0x000000
QSFP_PORT_1_3_INFO_REG
offset=0x007C
Total Offset =
0x10000A007C

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

Returns information from the QSFP1 Lane3.

# GPIO_ATR_REGMAP

## GPIO_ATR_REGS

Describes the behavior of GPIO lines when controlled by the ATR state.

### Offset 0x0000: ATR_STATE(15:0) Register Array (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
0x000000
ATR_STATE
offset=0x0000 + i*4
Cannot determine accessibility through this path
Total Offset =
0x00C000 + i*4

Initial Values

default | => | 0x00000000

This register is defined in HDL source file x4xx_gpio_atr.v.
It uses RegType GPIO_ATR_STATE which is defined in HDL source file x4xx_gpio_atr.v.

Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
Describes GPIO behavior for the different ATR states. When ATR_OPTION is set to use the DB states, TX and RX states for RF0 and RF1 are combined to create a single vector. This creates 16 different combinations, each with its own register. When ATR_OPTION is set to classic ATR, offsets 0x00-0x03 in this register group will be driven in accordance with the state of RF0, and offsets 0x04-0x07 will be driven in accordance with the state of RF1. CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05], TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]

Bits | Name
31..28 | Reserved
27..16 | GPIO_STATE_B (initialvalue=0)
15..12 | Reserved
11..0 | GPIO_STATE_A (initialvalue=0)

### Offset 0x0040: CLASSIC_ATR_CONFIG Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
0x000000
CLASSIC_ATR_CONFIG
offset=0x0040
Total Offset =
0x00C040

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_atr.v.

Controls the RF state mapping of each GPIO line when classic ATR mode is active.

Bits | Name
31..28 | Reserved
27..16 | RF_SELECT_B (initialvalue=0) Set which RF channel's state to reflect in the pins of HDMI connector B when ATR_OPTION is set to classic ATR. Controlled in a per-pin basis. 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
15..12 | Reserved
11..0 | RF_SELECT_A (initialvalue=0) Set which RF channel's state to reflect in the pins for HDMI connector A when ATR_OPTION is set to classic ATR. Controlled in a per-pin basis. 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)

### Offset 0x0044: ATR_OPTION_REGISTRER Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
0x000000
ATR_OPTION_REGISTRER
offset=0x0044
Total Offset =
0x00C044

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_atr.v.

Controls whether GPIO lines use the TX and RX state of an RF channel (Classic ATR) or the daughterboard state the selector for the ATR_STATE.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..1 | Reserved
0 | ATR_OPTION (initialvalue=0) Sets the scheme in which RF states in the radio will control GPIO lines. 0 = DB state is used. RF states are combined and the GPIO state is driven based on all 16 ATR_STATE registers. 1 = Each RF channel has its separate ATR state(Classic ATR). Use register CLASSIC_ATR_CONFIG to indicate the RF channel to which each GPIO line responds to.

### Offset 0x0048: GPIO_DIR Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
0x000000
GPIO_DIR
offset=0x0048
Total Offset =
0x00C048

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_atr.v.

Controls the direction of each GPIO signal when controlled by the radio state. 0 = GPIO pin set to input. 1 = GPIO pin set to output

Bits | Name
31..28 | Reserved
27..16 | GPIO_DIR_B (initialvalue=0)
15..12 | Reserved
11..0 | GPIO_DIR_A (initialvalue=0)

### Offset 0x004C: GPIO_DISABLED Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
0x000000
GPIO_DISABLED
offset=0x004C
Total Offset =
0x00C04C

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_atr.v.

Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.

Bits | Name
31..28 | Reserved
27..16 | GPIO_DISABLED_B (initialvalue=0)
15..12 | Reserved
11..0 | GPIO_DISABLED_A (initialvalue=0)

### Offset 0x0050: GPIO_IN Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
0x000000
GPIO_IN
offset=0x0050
Total Offset =
0x00C050

Initial Value = 0x00000000

This register is defined in HDL source file x4xx_gpio_atr.v.

Reflects the logic state of each GPIO input.

Bits | Name
31..28 | Reserved
27..16 | GPIO_IN_B (initialvalue=0)
15..12 | Reserved
11..0 | GPIO_IN_A (initialvalue=0)

# JTAG_REGMAP

## JTAG_REGS

This register map is present for each JTAG module.

Basic operation would be:

- poll ready until asserted
- write / read data
- write CONTROL register along with reset deasserted to start a transaction

For resetting the BITQ FSM, simply assert reset.

This operation seems a little strange, but it is what the axi_bitq driver expects. This behavior has been implemented in previous products.

### Offset 0x0000: TX_DATA Register (W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|JTAG_DB0
0x000060
TX_DATA
offset=0x0000
Total Offset =
0x1000088060
MB_CPLD_PL_REGMAP|JTAG_DB1
0x000080
Total Offset =
0x1000088080

Initial Value not specified

This register is defined in HDL source file ctrlport_to_jtag.v.

Data to be transmitted (TDI)

### Offset 0x0004: STB_DATA Register (W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|JTAG_DB0
0x000060
STB_DATA
offset=0x0004
Total Offset =
0x1000088064
MB_CPLD_PL_REGMAP|JTAG_DB1
0x000080
Total Offset =
0x1000088084

Initial Value not specified

This register is defined in HDL source file ctrlport_to_jtag.v.

Data to be transmitted (TMS)

### Offset 0x0008: CONTROL Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|JTAG_DB0
0x000060
CONTROL
offset=0x0008
Total Offset =
0x1000088068
MB_CPLD_PL_REGMAP|JTAG_DB1
0x000080
Total Offset =
0x1000088088

Initial Value = 0x00000001

This register is defined in HDL source file ctrlport_to_jtag.v.

JTAG module status and control

Bits | Name
31r | ready Bitq FSM is ready for input (no data transmission in progress).
31w | reset When asserted ('1') a soft-reset for the bitq FSM is triggered, preventing any transactions to take place. Deassert this bit, along with values for prescalar and length to trigger a new transaction (start strobe).
30..24 | Reserved
23..16 | Reserved
15..13 | Reserved
12..8 | length (Number of bits - 1) to be transferred
7..0 | prescalar (initialvalue=true) Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value.

### Offset 0x000C: RX_DATA Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|JTAG_DB0
0x000060
RX_DATA
offset=0x000C
Total Offset =
0x100008806C
MB_CPLD_PL_REGMAP|JTAG_DB1
0x000080
Total Offset =
0x100008808C

Initial Value not specified

This register is defined in HDL source file ctrlport_to_jtag.v.

Received data (TDO)

# MB_CPLD_PL_REGMAP

This register map is available using the PL CPLD SPI interface. All protocol masters controller by this register map are running with a clock frequency of 50 MHz.

## MB_CPLD_PL_WINDOWS

### Offset 0x0000: PL_REGISTERS Window (R|W)

Target regmap = PL_CPLD_BASE_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
PL_REGISTERS
offset=0x0000
size=0x40 (64 bytes)
Total Offset =
0x1000088000

This window is defined in HDL source file mb_cpld.v.

### Offset 0x0060: JTAG_DB0 Window (R|W)

Target regmap = JTAG_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
JTAG_DB0
offset=0x0060
size=0x20 (32 bytes)
Total Offset =
0x1000088060

This window is defined in HDL source file mb_cpld.v.

JTAG Master connected to first daugherboard's CPLD JTAG interface.

Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.

### Offset 0x0080: JTAG_DB1 Window (R|W)

Target regmap = JTAG_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
JTAG_DB1
offset=0x0080
size=0x20 (32 bytes)
Total Offset =
0x1000088080

This window is defined in HDL source file mb_cpld.v.

JTAG Master connected to second daugherboard's CPLD JTAG interface.

Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.

# NIXGE_REGMAP

## XGE_MAC_REGS

nixge (maps to 10g mac if present)

### Offset 0x0000: PORT_INFO Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
PORT_INFO
offset=0x0000
Total Offset =
0x1200008000
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018000
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028000
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038000
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048000
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058000
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068000
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078000

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Bits | Name
31..24 | COMPAT_NUM Constant indicating version for this space. Not used by the NIXGE driver (12/4/2020)
23..18 | Reserved
17 | ACTIVITY Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.
16 | LINK_UP Generically means that a connection with a peer has been established. Specific meaning varies based on the MGT_PROTOCOL.
15..8 | MGT_PROTOCOL Constant indicating what flavor of communication this port is using 0 = NONE 1 = 1GbE 2 = 10GbE 3 = Aurora 4 = WhiteRabbit 5 = 100GbE
7..0 | PORTNUM Constant indicating which port this register is hooked to 0 = QSFP0 1 = QSFP1

### Offset 0x0004: MAC_CTRL_STATUS Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
MAC_CTRL_STATUS
offset=0x0004
Total Offset =
0x1200008004
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018004
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028004
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038004
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048004
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058004
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068004
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078004

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Definition of this register depends on Protocol

10GBE

READ - Status

- 0 = status_crc_error
- 1 = status_fragment_error
- 2 = status_txdfifo_ovflow
- 3 = status_txdfifo_udflow
- 4 = status_rxdfifo_ovflow
- 5 = status_rxdfifo_udflow
- 6 = status_pause_frame_rx
- 7 = status_local_fault
- 8 = status_remote_fault

WRITE - Ctl

- 0 = ctrl_tx_enable

100 GBE

READ - Status

- 0 = tx_ovfout - Sets if TX overflow reported by CMAC (Stays set till MAC is reset). This is a fatal error
- 1 = tx_unfout - Sets if TX underflow reported by CMAC (Stays set till MAC is reset). This is a fatal error
- 2 = stat_rx_aligned - goes high when CMAC has finished alignment, and is ready to start reception of traffic.
- 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID) but upstream is trying to hold(TREADY)off we drop a packet. Upstream circuitry should detect this when traffic is forked between CHDR and CPU, so this bit will only set if there is a HW design error.
- 4 = auto_config_done - This bit goes high when the auto_config state machine finishes operation. It is very similiar to stat_rx_alligned, but waits for extra writes which occur after allignement to complete.
- 24:16 = pause_mask - readable version of pause_mask bellow.

WRITE - Ctl

- 0 = auto_enable - Defaults to ON after reset - Enables a state machine that performs CMAC register writes to bring up the MAC without SW intervention.
- 24:16 = pause_mask - A second layer of enables(the first being register in the CMAC) on the pause_request mechanic. Bits 7:0 of enable pause on PFC7:0. Bit 8 enables global pause request (not priority controlled). The mask is used for TX and RX.

### Offset 0x0008: MAC_PHY_STATUS Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
MAC_PHY_STATUS
offset=0x0008
Total Offset =
0x1200008008
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018008
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028008
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038008
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048008
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058008
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068008
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078008

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Definition of this register depends on Protocol

10GBE

*READ - Status *

- 0 = core_status 0 - link_up
- 1 = core_status 1
- 2 = core_status 2
- 3 = core_status 3
- 4 = core_status 4
- 5 = core_status 5
- 6 = core_status 6
- 7 = core_status 7

100 GBE

READ - Status

- 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
- 1 = usr_rx_reset - RX PLL's have locked

### Offset 0x000C: MAC_LED_CTL Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
MAC_LED_CTL
offset=0x000C
Total Offset =
0x120000800C
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001800C
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002800C
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003800C
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004800C
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005800C
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006800C
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007800C

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..2 | Reserved
1 | identify_value When identify_enable is set, this value controls the activity LED.
0 | identify_enable When set identify_value is used to control the activity LED. When clear the activity LED set on any TX or RX traffic to the mgt

### Offset 0x0010: ETH_MDIO_BASE Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
ETH_MDIO_BASE
offset=0x0010
Total Offset =
0x1200008010
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018010
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028010
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038010
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048010
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058010
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068010
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078010

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

The x4xx family of products does not use MDIO.

### Offset 0x0020: AURORA_OVERRUNS Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
AURORA_OVERRUNS
offset=0x0020
Total Offset =
0x1200008020
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018020
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028020
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038020
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048020
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058020
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068020
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078020

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Only valid if the protocol is Aurora.

### Offset 0x0024: AURORA_CHECKSUM_ERRORS Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
AURORA_CHECKSUM_ERRORS
offset=0x0024
Total Offset =
0x1200008024
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018024
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028024
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038024
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048024
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058024
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068024
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078024

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Only valid if the protocol is Aurora.

### Offset 0x0028: AURORA_BIST_CHECKER_SAMPS Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
AURORA_BIST_CHECKER_SAMPS
offset=0x0028
Total Offset =
0x1200008028
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018028
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028028
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038028
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048028
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058028
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068028
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078028

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Only valid if the protocol is Aurora.

### Offset 0x002C: AURORA_BIST_CHECKER_ERRORS Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
AURORA_BIST_CHECKER_ERRORS
offset=0x002C
Total Offset =
0x120000802C
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001802C
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002802C
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003802C
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004802C
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005802C
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006802C
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007802C

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Only valid if the protocol is Aurora.

## XGE_MAC_WINDOW

### Offset 0x1000: XGE_MAC Window (R|W)

Target regmap = XGE_MAC_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|NIXGE
0x008000
XGE_MAC
offset=0x1000
size=0x1000 (4 Kbytes)
Total Offset =
0x1200009000
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200019000
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200029000
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200039000
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200049000
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200059000
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200069000
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200079000

This window is defined in HDL source file uhd_regs.v.

# PL_CPLD_BASE_REGMAP

## MB_CPLD_LED_REGS

Register Map to control QSFP LEDs.

### Offset 0x0020: LED_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|PL_REGISTERS
0x000000
LED_REGISTER
offset=0x0020
Total Offset =
0x1000088020

Initial Value not specified

This register is defined in HDL source file pl_cpld_regs.v.

Provides to the LEDs of the QSFP ports. Write access will directly change the LED status. The LED lights up if the corresponding bit is set.

Bits | Name
15..12 | QSFP1_LED_ACTIVE Active LEDs of QSFP port 1
11..8 | QSFP1_LED_LINK Link LEDs of QSFP port 1
7..4 | QSFP0_LED_ACTIVE Active LEDs of QSFP port 0
3..0 | QSFP0_LED_LINK Link LEDs of QSFP port 0

## PL_CMI_REGS

Cable present status register.

### Offset 0x0030: CABLE_PRESENT_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|PL_REGISTERS
0x000000
CABLE_PRESENT_REG
offset=0x0030
Total Offset =
0x1000088030

Initial Value not specified

This register is defined in HDL source file pl_cpld_regs.v.

Information from FPGA about the cable present status.

Bits | Name
1 | IPASS1_CABLE_PRESENT Set to 1 if cable present in iPass 1 connector.
0 | IPASS0_CABLE_PRESENT Set to 1 if cable present in iPass 0 connector.

## PL_CPLD_BASE_REGS

Basic registers containing version and capabilities information.

### Offset 0x0000: SIGNATURE_REGISTER Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|PL_REGISTERS
0x000000
SIGNATURE_REGISTER
offset=0x0000
Total Offset =
0x1000088000

Initial Value not specified

This register is defined in HDL source file pl_cpld_regs.v.

Contains the product's signature.

Bits | Name
31..0 | PRODUCT_SIGNATURE Fixed value PL_CPLD_SIGNATURE of CONSTANTS_REGMAP

### Offset 0x0004: REVISION_REGISTER Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|PL_REGISTERS
0x000000
REVISION_REGISTER
offset=0x0004
Total Offset =
0x1000088004

Initial Value not specified

This register is defined in HDL source file pl_cpld_regs.v.

Contains the CPLD revision (see CPLD_REVISION of CONSTANTS_REGMAP)

Bits | Name
31..24 | REVISION_YY Contains revision year code.
23..16 | REVISION_MM Contains revision month code.
15..8 | REVISION_DD Contains revision day code.
7..0 | REVISION_HH Contains revision hour code.

### Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|PL_REGISTERS
0x000000
OLDEST_COMPATIBLE_REVISION_REGISTER
offset=0x0008
Total Offset =
0x1000088008

Initial Value not specified

This register is defined in HDL source file pl_cpld_regs.v.

This register returns (in YYMMDDHH format) the oldest revision that is still compatible with this one. Compatible means that registers or register bits may have been added, but not modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).

Bits | Name
31..24 | OLD_REVISION_YY Contains revision year code.
23..16 | OLD_REVISION_MM Contains revision month code.
15..8 | OLD_REVISION_DD Contains revision day code.
7..0 | OLD_REVISION_HH Contains revision hour code.

### Offset 0x000C: SCRATCH_REGISTER Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|PL_REGISTERS
0x000000
SCRATCH_REGISTER
offset=0x000C
Total Offset =
0x100008800C

Initial Value not specified

This register is defined in HDL source file pl_cpld_regs.v.

Read/write register for general software use.

### Offset 0x0010: GIT_HASH_REGISTER Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
PL_CPLD_REGMAP|MB_CPLD
0x008000
MB_CPLD_PL_REGMAP|PL_REGISTERS
0x000000
GIT_HASH_REGISTER
offset=0x0010
Total Offset =
0x1000088010

Initial Value not specified

This register is defined in HDL source file pl_cpld_regs.v.

Git hash of commit used to build this image.
Value equals 0xDEADBEEF if the git hash was not used during synthesis.

Bits | Name
31..28 | GIT_CLEAN 0x0 in case the git status was clean 0xF in case there were uncommitted changes
27..0 | GIT_HASH 7 hex digit hash code of the commit

# PL_CPLD_REGMAP

This register map is available from the PS via AXI and MPM endpoint. Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.

## PL_CPLD_WINDOWS

### Offset 0x0000: BASE Window (R|W)

Target regmap = CPLD_INTERFACE_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
BASE
offset=0x0000
size=0x40 (64 bytes)
Total Offset =
0x1000080000

This window is defined in HDL source file cpld_interface.v.

### Offset 0x8000: MB_CPLD Window (R|W)

Target regmap = MB_CPLD_PL_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
MB_CPLD
offset=0x8000
size=0x8000 (32 Kbytes)
Total Offset =
0x1000088000

This window is defined in HDL source file cpld_interface.v.

All registers of the MB CPLD (PL part).

### Offset 0x10000: DB0_CPLD Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
DB0_CPLD
offset=0x10000
size=0x8000 (32 Kbytes)
Total Offset =
0x1000090000

This window is defined in HDL source file cpld_interface.v.

All registers of the first DB CPLD. Register map will be added later on.

### Offset 0x18000: DB1_CPLD Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|MPM_ENDPOINT
0x1000080000
DB1_CPLD
offset=0x18000
size=0x8000 (32 Kbytes)
Total Offset =
0x1000098000

This window is defined in HDL source file cpld_interface.v.

All registers of the second DB CPLD. Register map will be added later on.

# PL_DMA_MASTER_REGMAP

This is a regmap to document the different ports that have access to the PS system memory. Each port may have different restrictions on system memory. See the corresponding window for details

## HPC0_DMA

### Offset 0x0000: AXI_HPC0_WINDOW Window (R|W)

Target port = X410_FPGA|ARM_S_AXI_HPC0

(show extended info)

AXI_HPC0_WINDOW
offset=0x0000
size=0x10000000000 (1024 Gbytes)

This window is defined in HDL source file common_regs.v.

The HPC0 port of the PS is used for general purpose cache-coherent accesses to the PS system memory. Different applications may use it for different purposes. Its access is configured as follows:

Offset | Size | Description
--- | --- | ---
0x000800000000 | 0x000800000000 | DDR_HIGH
0x00000000 | 0x80000000 | DDR_LOW
0xFF000000 | 0x01000000 | LPS_OCM
0xC0000000 | 0x20000000 | QSPI

## HPC1_DMA

### Offset 0x0000: AXI_HPC1_WINDOW Window (R|W)

Target port = X410_FPGA|ARM_S_AXI_HPC1

(show extended info)

AXI_HPC1_WINDOW
offset=0x0000
size=0x1000000000 (64 Gbytes)

This window is defined in HDL source file common_regs.v.

The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx. Its access is configured as follows:

Offset | Size | Description
--- | --- | ---
0x000800000000 | 0x000800000000 | DDR_HIGH
0x00000000 | 0x80000000 | DDR_LOW
0xC0000000 | 0x20000000 | QSPI

# PS_CPLD_BASE_REGMAP

## DIO_REGS

Registers to control the GPIO buffer direction on the DIO board connected to the FPGA. Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. Set the direction in the FPGA's DIO register appropriately.

### Offset 0x0030: DIO_DIRECTION_REGISTER Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
DIO_DIRECTION_REGISTER
offset=0x0030
Total Offset =
0x000030

Initial Value = 0x00000000

This register is defined in HDL source file ps_cpld_regs.v.

Set the direction of FPGA buffer connected to DIO ports on the DIO board.
Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.

Bits | Name
31..28 | Reserved
27..16 | DIO_DIRECTION_B (initialvalue=0)
15..12 | Reserved
11..0 | DIO_DIRECTION_A (initialvalue=0)

## PS_CMI_REGS

Cable present status register.

### Offset 0x0034: SERIAL_NUM_LOW_REG Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
SERIAL_NUM_LOW_REG
offset=0x0034
Total Offset =
0x000034

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Least significant bytes of 5 byte serial number.

### Offset 0x0038: SERIAL_NUM_HIGH_REG Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
SERIAL_NUM_HIGH_REG
offset=0x0038
Total Offset =
0x000038

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Most significant byte of 5 byte serial number.

### Offset 0x003C: CMI_CONTROL_STATUS Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
CMI_CONTROL_STATUS
offset=0x003C
Total Offset =
0x00003C

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Control CMI communication and delivers information on the CMI link status.

Bits | Name
31r | OTHER_SIDE_DETECTED 1 if an upstream CMI device has been detected.
30..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..1 | Reserved
0 | CMI_READY Set if the device is ready to establish a PCI-Express link (affects CMI_CLP_READY bit).

## PS_CONTROL_REGS

Register Map to control MB CPLD functions.

### Offset 0x0020: PL_DB_REGISTER Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
PL_DB_REGISTER
offset=0x0020
Total Offset =
0x000020

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Register to control the PL part DB SPI connection and reset generation. The DB connection is clocked with PLL reference clock. Ensure this clock is stable and enabled before starting any SPI request. The PLL reference clock can be disabled if both DB connections are disabled or inactive. To enable the DB connection, enable clock with one write access and release reset with the next write access. To disable the DB connection, assert reset with one write access and disable clocks with the next write access.

Bits | Name
31..24 | Reserved
23..22 | Reserved
21w | ASSERT_RESET_DB1 Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1)
20w | ASSERT_RESET_DB0 Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0)
19..18 | Reserved
17w | RELEASE_RESET_DB1 Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1)
16w | RELEASE_RESET_DB0 Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0)
15 | Reserved
14w | DISABLE_PLL_REF_CLOCK Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock.
13w | DISABLE_CLOCK_DB1 Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1)
12w | DISABLE_CLOCK_DB0 Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0)
11 | Reserved
10w | ENABLE_PLL_REF_CLOCK Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK)
9w | ENABLE_CLOCK_DB1 Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1)
8w | ENABLE_CLOCK_DB0 Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0)
7..6 | Reserved
5r | DB1_RESET_ASSERTED Indicates that reset is asserted for DB 1.
4r | DB0_RESET_ASSERTED Indicates that reset is asserted for DB 0.
3 | Reserved
2r | PLL_REF_CLOCK_ENABLED Indicates if the PLL reference clock for the PL interface is enabled.
1r | DB1_CLOCK_ENABLED Indicates if a clock is forwarded to DB 1.
0r | DB0_CLOCK_ENABLED Indicates if a clock is forwarded to DB 0.

## PS_CPLD_BASE_REGS

Basic registers containing version and capabilites information.

### Offset 0x0000: SIGNATURE_REGISTER Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
SIGNATURE_REGISTER
offset=0x0000
Total Offset =
0x000000

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Contains the product's signature.

Bits | Name
31..0 | PRODUCT_SIGNATURE Fixed value PS_CPLD_SIGNATURE of CONSTANTS_REGMAP

### Offset 0x0004: REVISION_REGISTER Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
REVISION_REGISTER
offset=0x0004
Total Offset =
0x000004

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Contains the CPLD revision (see CPLD_REVISION of CONSTANTS_REGMAP).

Bits | Name
31..24 | REVISION_YY Contains revision year code.
23..16 | REVISION_MM Contains revision month code.
15..8 | REVISION_DD Contains revision day code.
7..0 | REVISION_HH Contains revision hour code.

### Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
OLDEST_COMPATIBLE_REVISION_REGISTER
offset=0x0008
Total Offset =
0x000008

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

This register returns (in YYMMDDHH format) the oldest revision that is still compatible with this one. Compatible means that registers or register bits may have been added, but not modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).

Bits | Name
31..24 | OLD_REVISION_YY Contains revision year code.
23..16 | OLD_REVISION_MM Contains revision month code.
15..8 | OLD_REVISION_DD Contains revision day code.
7..0 | OLD_REVISION_HH Contains revision hour code.

### Offset 0x000C: SCRATCH_REGISTER Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
SCRATCH_REGISTER
offset=0x000C
Total Offset =
0x00000C

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Read/write register for general software use.

### Offset 0x0010: GIT_HASH_REGISTER Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|PS_REGISTERS
0x000000
GIT_HASH_REGISTER
offset=0x0010
Total Offset =
0x000010

Initial Value not specified

This register is defined in HDL source file ps_cpld_regs.v.

Git hash of commit used to build this image.
Value equals 0xDEADBEEF if the git hash was not used during synthesis.

Bits | Name
31..28 | GIT_CLEAN 0x0 in case the git status was clean 0xF in case there were uncommitted changes
27..0 | GIT_HASH 7 hex digit hash code of the commit

# PS_POWER_REGMAP

## PS_POWER_REGS

Registers to control power supplies on the motherboard.

### Offset 0x0000: IPASS_POWER_REG Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|POWER_REGISTERS
0x000060
IPASS_POWER_REG
offset=0x0000
Total Offset =
0x000060

Initial Value not specified

This register is defined in HDL source file ps_power_regs.v.

Controls the power supplies for the iPass connectors.

Bits | Name
31r | IPASS_POWER_FAULT1 Asserted signal indicates a power fault in power switch for iPass connector 1. Sticky bit. Asserted on occurrence. Reset using IPASS_CLEAR_POWER_FAULT1.
31w | IPASS_CLEAR_POWER_FAULT1 Clear IPASS_POWER_FAULT1.
30r | IPASS_POWER_FAULT0 Asserted signal indicates a power fault in power switch for iPass connector 0. Sticky bit. Asserted on occurrence. Reset using IPASS_CLEAR_POWER_FAULT0.
30w | IPASS_CLEAR_POWER_FAULT0 Clear IPASS_POWER_FAULT0.
29..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..1 | Reserved
0 | IPASS_DISABLE_POWER_BIT Set to 1 to disable power for both iPass connectors.

### Offset 0x0004: OSC_POWER_REG Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|POWER_REGISTERS
0x000060
OSC_POWER_REG
offset=0x0004
Total Offset =
0x000064

Initial Value not specified

This register is defined in HDL source file ps_power_regs.v.

Controls the power supplies for the oscillators.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..2 | Reserved
1 | OSC_122_88 Enables 5V power switch for the 122.88 MHz oscillator.
0 | OSC_100 Enables 5V power switch for the 100 MHz oscillator.

# QSFP_REGMAP

## QSFP_WINDOWS

Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations

- 1X10GB Ethernet - Using OpenCore XGE MAC
- 1x100GB Ethernet - Using Xilinx CMAC
- (future possible) - Xilinx Aurora (various rates and lane widths)
- (future possible) - 4X10GB Ethernet

### Offset 0x0000: ETH_DMA Window (R|W)

Target regmap = DMA_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
ETH_DMA
offset=0x0000
size=0x4000 (16 Kbytes)
Total Offset =
0x1200000000
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200010000
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200020000
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200030000
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200040000
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200050000
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200060000
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200070000

This window is defined in HDL source file uhd_regs.v.

### Offset 0x8000: NIXGE Window (R|W)

Target regmap = NIXGE_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
NIXGE
offset=0x8000
size=0x2000 (8 Kbytes)
Total Offset =
0x1200008000
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x1200018000
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x1200028000
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x1200038000
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x1200048000
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x1200058000
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x1200068000
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x1200078000

This window is defined in HDL source file uhd_regs.v.

### Offset 0xA000: UIO Window (R|W)

Target regmap = UIO_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
UIO
offset=0xA000
size=0x2000 (8 Kbytes)
Total Offset =
0x120000A000
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A000
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A000
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A000
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A000
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A000
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A000
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A000

This window is defined in HDL source file uhd_regs.v.

### Offset 0xC000: CMAC Window (R|W)

Target regmap = CMAC_REGMAP

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
CMAC
offset=0xC000
size=0x2000 (8 Kbytes)
Total Offset =
0x120000C000
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001C000
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002C000
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003C000
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004C000
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005C000
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006C000
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007C000

This window is defined in HDL source file uhd_regs.v.

# RADIO_CTRLPORT_REGMAP

## RADIO_CTRLPORT_WINDOWS

Each radio's CtrlPort peripheral interface is divided into the following memory spaces. Note that the CtrlPort peripheral interface starts at offset 0x80000 in the RFNoC Radio block's register space. The following diagram displays the distribution of the CtrlPort interface to the different modules it interacts with.

### Offset 0x0000: DB_WINDOW Window (R|W)

(show extended info)

DB_WINDOW
offset=0x0000
size=0x8000 (32 Kbytes)

This window is defined in HDL source file x4xx_core_common.v.

Daughterboard GPIO interface. Register access within this space is directed to the associated daughterboard CPLD.

### Offset 0x8000: RFDC_TIMING_WINDOW Window (R|W)

Target regmap = RFDC_TIMING_REGMAP

(show extended info)

RFDC_TIMING_WINDOW
offset=0x8000
size=0x4000 (16 Kbytes)

This window is defined in HDL source file x4xx_core_common.v.

RFDC timing control interface.

### Offset 0xC000: DIO_WINDOW Window (R|W)

Target regmap = RADIO_DIO_REGMAP

(show extended info)

DIO_WINDOW
offset=0xC000
size=0x4000 (16 Kbytes)

This window is defined in HDL source file x4xx_core_common.v.

DIO control interface. Interacts with the DIO source selection block, ATR-based DIO control and the DIO digital interface

# RADIO_DIO_REGMAP

This map contains register windows for controlling the different sources that drive the state of DIO lines.

## DIO_SOURCES

### Offset 0x0000: RADIO_GPIO_ATR_REGS Window (R|W)

Target regmap = GPIO_ATR_REGMAP

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
RADIO_GPIO_ATR_REGS
offset=0x0000
size=0x1000 (4 Kbytes)
Total Offset =
0x00C000

This window is defined in HDL source file x4xx_core_common.v.

Contains controls for DIO behavior based on the ATR state of the accessed radio

### Offset 0x1000: DIO_SOURCE_CONTROL Window (R|W)

Target regmap = DIO_REGMAP

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
DIO_SOURCE_CONTROL
offset=0x1000
size=0x1000 (4 Kbytes)
Total Offset =
0x00D000

This window is defined in HDL source file x4xx_core_common.v.

Window to access the DIO register map through the control port from the radio blocks.

### Offset 0x2000: DIGITAL_IFC_REGS Window (R|W)

Target regmap = DIG_IFC_REGMAP

(show extended info)

RADIO_CTRLPORT_REGMAP|DIO_WINDOW
0x00C000
DIGITAL_IFC_REGS
offset=0x2000
size=0x1000 (4 Kbytes)
Total Offset =
0x00E000

This window is defined in HDL source file x4xx_core_common.v.

Register space reserved for configuring a digital interface over the GPIO lines. Currently, SPI is the only supported protocol.

# RECONFIG_REGMAP

## RECONFIG_REGS

These registers are used to upload and verify a new primary image to the Max 10 FPGA on-chip flash when configured to support dual configuration images. The steps below outline the process of verifying/preparing the new image to be written, erasing the current image, writing the new image, and verifying the new image was successfully written.

Prepare the data...

1. The Max 10 FPGA build should generate a *cfm0_auto.rpd file The *.rpd file is a "raw programming data" file holding all data related to the configuration image (CFM0). There are two important items to note regarding the addresses. First the *rpd data uses byte addresses. Second, the start/end addresses defined by FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses

2. As a sanity check, verify the size of the raw programming data for CFM0 correspond to the address range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by reading the values from FLASH_CFM0_START_ADDR_REG and FLASH_CFM0_END_ADDR, subtract both values, add one and multiply by four.

3. Having passed the sanity check the *.rpd data must now be manipulated into the form required by Altera's on-chip flash IP. Two operations must be performed. First the data must be converted from bytes to 32-bit words. Second the bit order must be reversed. This is illustrated in in the following table which shows byte address and data from the *.rpd file compared to the word address and data to be written to the on-chip flash.

   .Map Addr | .Map Data | Flash Addr | Flash Data
   0x2B800 | 0x01 | 0xAC00 | 0x8040C020
   0x2B801 | 0x02
   0x2B802 | 0x03
   0x2B803 | 0x04
   0x2B804 | 0x05 | 0xAC01 | 0xA060E010
   0x2B805 | 0x06
   0x2B806 | 0x07
   0x2B807 | 0x08

4. The resulting set of flash address data pairs should be used when writing FLASH_ADDR_REG and FLASH_WRITE_DATA_REG to update the CFM0 image. However, prior to writing the new image the old image must be erased.

Erase the current primary flash image...

1. Read FLASH_STATUS_REG and verify no error bits are asserted and that all read, write, and erase operations are idle.

2. Disable write protection of the flash by strobing the FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.

3. Verify write protection is disabled and no errors are present by reading FLASH_STATUS_REG.

4. Initiate the erase operation by setting FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of FLASH_CONTROL_REG.

5. Poll the FLASH_ERASE_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the erase operation is complete, then verify the operation was successful by checking that the FLASH_ERASE_ERR bit is de-asserted. Erase operations are expected to take a maximum of 350 msec. Upon completion of the erase operation write protection will remain disabled.

6. Erase additional sectors as required (see FLASH_ERASE_SECTOR for details) by restarting with first step.

Write the new primary flash image...

1. Read FLASH_STATUS_REG and verify no error bits are asserted, all read, write, and erase operations are idle, and write protection is disabled.

2. Set the target address for the write to the Max 10 on-chip flash by writing value from FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

3. Set the data to be written to this address by writing the new 32-bit word of the new image to FLASH_WRITE_DATA_REG.

4. Initiate the write by strobing FLASH_WRITE_STB of FLASH_CONTROL_REG.

5. Poll the FLASH_WRITE_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the write operation is complete, then verify the operation was successful by checking that the FLASH_WRITE_ERR bit is de-asserted. Write operations are expected to take a maximum of 550 usec.

6. Upon completion of the write operation return to step 2, incrementing the target address by one, and writing the next 32-bit word to Max10FlashWriteDatReg. If this was the last write, indicated by writing to FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step to enable write protection.

7. After writing the new image enable write protection by strobing the FLASH_ENABLE_WP_STB bit of FLASH_CONTROL_REG.

Verify the new primary flash image...

1. Read FLASH_STATUS_REG and verify no error bits are asserted and that all read, write, and erase operations are idle.

2. Set the target address for the read in the Max 10 on-chip flash by writing value from FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

3. Initiate the read by strobing FLASH_READ_STB of FLASH_CONTROL_REG.

4. Poll the FLASH_READ_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the read operation is complete, then verify the operation was successful by checking that the FLASH_READ_ERR bit is de-asserted. There is no guidance on exactly how long reads take to complete, but they are expected to be fairly quick. A very conservative timeout on this polling would be similar to that used for write operations.

5. Upon completion of the read operation the resulting data returned by the on-chip flash will be available in Max10FlashReadDatReg. Read this register, compare to expected value previously written, and ensure they match.

6. Return to step 2, incrementing the target address by one. If this was the last read verification is complete and no further action is required.

After the flash has been erased, programmed, and verified, a power cycle is required for the new image to become active.

### FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration

These values are the start and end address of the CFM image flash sector from Intel's On-Chip Flash IP Generator. Be aware that three different values exist per each of the two supported MAX10 variants: 10M04 and 10M08 Note that the values given in the IP generator are byte based where the values of this enum are U32 based (divided by 4).

Value | Name
Dec | Hex
4096 | 0x01000 | FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04
8192 | 0x02000 | FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08
39936 | 0x09C00 | FLASH_PRIMARY_IMAGE_START_ADDR_10M04
44032 | 0x0AC00 | FLASH_PRIMARY_IMAGE_START_ADDR_10M08
75775 | 0x127FF | FLASH_PRIMARY_IMAGE_END_ADDR_10M04
79871 | 0x137FF | FLASH_PRIMARY_IMAGE_END_ADDR_10M08

This enumerated type is defined in HDL source file reconfig_engine.v.

### Offset 0x0000: FLASH_STATUS_REG Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|RECONFIG
0x000040
FLASH_STATUS_REG
offset=0x0000
Total Offset =
0x000040

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..24 | Reserved
23..17 | Reserved
16 | FLASH_MEM_INIT_ENABLED This bit is asserted when the flash can hold an image with memory initialization.
15..14 | Reserved
13 | FLASH_WRITE_ERR This bit is asserted when write operation fails. Clear this error by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In the event of a write error... the primary configuration image may be corrupted, and power cycling the board may result unknown behavior. write protection of the flash will automatically be re-enabled. attempts to disable write protection will be ignored. attempts to read/write/erase the flash will be ignored.
12 | FLASH_WRITE_IDLE This bit is de-asserted when a write operation is in progress. Poll this bit after strobing the FLASH_WRITE_STB bit of FLASH_CONTROL_REG to determine when the write operation has completed, then check the FLASH_WRITE_ERR bit to verify the operation was successful.
11..10 | Reserved
9 | FLASH_ERASE_ERR This bit is asserted when an erase operation fails. Clear this error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In the event of an erase error... the primary configuration image may be corrupted, and power cycling the board may result in unknown behavior. write protection of the flash will automatically be re-enabled. attempts to disable write protection will be ignored. attempts to read/write/erase the flash will be ignored.
8 | FLASH_ERASE_IDLE This bit is de-asserted when an erase operation is in progress. Poll this bit after strobing the FLASH_ERASE_STB bit of FLASH_CONTROL_REG to determine when the erase operation has completed, then check the FLASH_ERASE_ERR bit to verify the operation was successful.
7..6 | Reserved
5 | FLASH_READ_ERR This bit is asserted when a read operation fails. Clear this error by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the event of a read error... the data in FLASH_READ_DATA_REG is invalid. attempts to disable write protection will be ignored. attempts to read/write/erase the flash will be ignored.
4 | FLASH_READ_IDLE This bit is de-asserted when a read operation is in progress. Poll this bit after strobing the FLASH_READ_STB bit of FLASH_CONTROL_REG to determine when the read operation has completed, then check the FLASH_READ_ERR bit to verify the operation was successful.
3..1 | Reserved
0 | FLASH_WP_ENABLED This bit is asserted when the flash is write protected and de-asserted when write protection is disabled. Write protection must be enabled prior to performing read operations. Write protection must be disabled prior to performing write and erase operations.

### Offset 0x0004: FLASH_CONTROL_REG Register (W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|RECONFIG
0x000040
FLASH_CONTROL_REG
offset=0x0004
Total Offset =
0x000044

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..11 | Reserved
10w | CLEAR_FLASH_ERASE_ERROR_STB (Strobe) Strobe this bit to clear an erase error.
9w | CLEAR_FLASH_WRITE_ERROR_STB (Strobe) Strobe this bit to clear a write error.
8w | CLEAR_FLASH_READ_ERROR_STB (Strobe) Strobe this bit to clear a read error.
7..5w | FLASH_ERASE_SECTOR (Strobe) Defines the sector to be erased. Has to be set latest with the write access which starts the erase operation by strobing FLASH_ERASE_STB. With 10M04 variants, if the flash is configured to support memory initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2 to 4 have to be erased. If the flag is not asserted only sector 4 has to be erased. With 10M08 variants, the sectors to be erased are 3 to 5 when using memory initialization or only sector 5 otherwise.
4w | FLASH_ERASE_STB (Strobe) Strobe this bit to erase the primary Max10 configuration image (CFM0). Prior to strobing this bit verify no other write or erase operations are in progress, write protection is disabled, and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to erase the primary image while other write or erase operations are in progress will be ignored. Attempts to erase the primary image when write protection is enabled will be ignored. Strobing this bit and FLASH_WRITE_STB simultaneously will result both the erase and the write operation being ignored, both corresponding error bits being set, and write protection being re-enabled. After strobing this bit poll the FLASH_ERASE_IDLE and FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when the erase operation is complete and if it was successful.
3w | FLASH_WRITE_STB (Strobe) Strobe this bit to write the data contained in FLASH_WRITE_DATA_REG to the flash address identified in FLASH_ADDR_REG. The flash must be erased before writing new data. Prior to strobing this bit verify write protection is disabled, no other write or erase operations are in progress, and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to write data while other write or erase operations are in progress will be ignored. Attempts to write data with write protection enabled will be ignored. Strobing this bit and FLASH_ERASE_STB simultaneously will result in both the write and erase operation being ignored, both corresponding error bits being set, and write protection being re-enabled. After strobing this bit poll theMax10FlashWriteIdle and FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when the write operation is complete and if it was successful.
2w | FLASH_READ_STB (Strobe) Strobe this bit to read data from the flash address identified in FLASH_ADDR_REG. Prior to strobing this bit verify no read, write, or erase operations are in progress, no error bits are asserted, and write protection is enabled by reading FLASH_STATUS_REG. Attempts to read data while other operations are in progress or while write protection is disabled will be ignored. After strobing this bit poll the FLASH_READ_IDLE and FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when the read operation is complete and if it was successful. Upon successful completion the data read from flash will be available in FLASH_READ_DATA_REG.
1w | FLASH_DISABLE_WP_STB (Strobe) Strobe this bit to disable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to determine the current state of write protection. Prior to strobing this bit verify no read operations are in progress and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to disable write protection while a read is in progress will be ignored. Attempts to disable write protection will be ignored if this bit is strobed simultaneously with either FLASH_READ_STB or FLASH_ENABLE_WP_STB. Write protection must be disabled prior to performing erase or write operations. Upon completion of erase/write operations write protection will remain disabled. When not actively erasing or writing a new image write protection should be enabled to avoid data corruption.
0w | FLASH_ENABLE_WP_STB (Strobe) Strobe this bit to enable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to determine the current state of write protection. Prior to strobing this bit verify no write or erase operations are in progress and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to enable write protection while erase or write operations are in progress will be ignored. Write protection must be enabled prior to performing read operations. Write protection should be enabled after completing write or erase operations to prevent data corruption.

### Offset 0x0008: FLASH_ADDR_REG Register (R|W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|RECONFIG
0x000040
FLASH_ADDR_REG
offset=0x0008
Total Offset =
0x000048

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..24 | Reserved
23..17 | Reserved
16..0 | FLASH_ADDR This field holds the target address for the next read or write operation. Set this field prior to strobing the FLASH_WRITE_STB and FLASH_READ_STB bits of FLASH_CONTROL_REG. Valid addresses are defined by the FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.

### Offset 0x000C: FLASH_WRITE_DATA_REG Register (W)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|RECONFIG
0x000040
FLASH_WRITE_DATA_REG
offset=0x000C
Total Offset =
0x00004C

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0w | FLASH_WRITE_DATA Data in this register will be written to the flash at the address identified in FLASH_ADDR_REG when a successful write operation is executed.

### Offset 0x0010: FLASH_READ_DATA_REG Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|RECONFIG
0x000040
FLASH_READ_DATA_REG
offset=0x0010
Total Offset =
0x000050

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0 | FLASH_READ_DATA This register contains data read from the flash address identified in FLASH_ADDR_REG after a successful read operation is executed.

### Offset 0x0014: FLASH_CFM0_START_ADDR_REG Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|RECONFIG
0x000040
FLASH_CFM0_START_ADDR_REG
offset=0x0014
Total Offset =
0x000054

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0 | FLASH_CFM0_START_ADDR Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

### Offset 0x0018: FLASH_CFM0_END_ADDR_REG Register (R)

(show extended info)

Port ARM_SPI1_CS3
MB_CPLD_PS_REGMAP|RECONFIG
0x000040
FLASH_CFM0_END_ADDR_REG
offset=0x0018
Total Offset =
0x000058

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0 | FLASH_CFM0_END_ADDR Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

# RFDC_REGS_REGMAP

## RFDC_REGS

These are the registers located within the RFDC block design that provide control and status support for the RF chain.

### FABRIC_DSP_BW_ENUM Enumeration

Value | Name
Dec | Hex
0 | 0x000 | FABRIC_DSP_BW_NONE
100 | 0x064 | FABRIC_DSP_BW_100M
200 | 0x0C8 | FABRIC_DSP_BW_200M
400 | 0x190 | FABRIC_DSP_BW_400M
1000 | 0x3E8 | FABRIC_DSP_BW_FULL

This enumerated type is defined in HDL source file common_regs.v.

### Offset 0x0000: MMCM Window (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
MMCM
offset=0x0000
size=0x10000 (64 Kbytes)
Total Offset =
0x1000140000

This window is defined in HDL source file x410_rfdc_regs.v.

Register space for controlling the data clock MMCM instance within the RFDC block design. Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the regiter space description in chapter 2. (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)

### Offset 0x10000: INVERT_DB0_IQ_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
INVERT_DB0_IQ_REG
offset=0x10000
Total Offset =
0x1000150000

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

Control register for inverting I/Q data.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | Reserved
11 | INVERT_DB0_DAC3_IQ
10 | INVERT_DB0_DAC2_IQ
9 | INVERT_DB0_DAC1_IQ
8 | INVERT_DB0_DAC0_IQ
7..4 | Reserved
3 | INVERT_DB0_ADC3_IQ
2 | INVERT_DB0_ADC2_IQ
1 | INVERT_DB0_ADC1_IQ
0 | INVERT_DB0_ADC0_IQ

### Offset 0x10800: INVERT_DB1_IQ_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
INVERT_DB1_IQ_REG
offset=0x10800
Total Offset =
0x1000150800

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

Control register for inverting I/Q data.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | Reserved
11 | INVERT_DB1_DAC3_IQ
10 | INVERT_DB1_DAC2_IQ
9 | INVERT_DB1_DAC1_IQ
8 | INVERT_DB1_DAC0_IQ
7..4 | Reserved
3 | INVERT_DB1_ADC3_IQ
2 | INVERT_DB1_ADC2_IQ
1 | INVERT_DB1_ADC1_IQ
0 | INVERT_DB1_ADC0_IQ

### Offset 0x11000: MMCM_RESET_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
MMCM_RESET_REG
offset=0x11000
Total Offset =
0x1000151000

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

Control register for resetting the data clock MMCM.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..1 | Reserved
0 | RESET_MMCM Write a '1' to this bit to reset the MMCM. Then write a '0' to place the MMCM out of reset.

### Offset 0x12000: RF_RESET_CONTROL_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
RF_RESET_CONTROL_REG
offset=0x12000
Total Offset =
0x1000152000

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.
It uses RegType RF_RESET_CONTROL_REGTYPE which is defined in HDL source file common_regs.v.

Control register for the RF reset controller. Verify the FSM ID before polling starting any reset sequence. To use the SW reset triggers: Wait until DB*_DONE is de-asserted. Assert either the *_RESET or *_ENABLE bitfields. Wait until DB*_DONE is asserted to release the trigger. The DB*_DONE signal should then de-assert.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..10 | Reserved
9 | DAC_ENABLE Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted.
8 | DAC_RESET Write a '1' to this bit to trigger a reset for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted.
7..6 | Reserved
5 | ADC_ENABLE Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted.
4 | ADC_RESET Write a '1' to this bit to trigger a reset for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted.
3..1 | Reserved
0 | FSM_RESET Write a '1' to this bit to reset the RF reset controller. Write a '0' once db0_fsm_reset_done asserts.

### Offset 0x12008: RF_RESET_STATUS_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
RF_RESET_STATUS_REG
offset=0x12008
Total Offset =
0x1000152008

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.
It uses RegType RF_RESET_STATUS_REGTYPE which is defined in HDL source file common_regs.v.

Status register for the RF reset controller. Verify the FSM ID before polling starting any reset sequence. Refer to RF*_RESET_CONTROL_REG for instructions on how to use the status bits in this register.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | Reserved
11 | DAC_SEQ_DONE This bit asserts ('1') when the DB0 DAC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset).
10..8 | Reserved
7 | ADC_SEQ_DONE This bit asserts ('1') when the DB0 ADC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset).
6..4 | Reserved
3 | FSM_RESET_DONE This bit asserts ('1') when the DB0 RF reset controller FSM reset sequence is completed. The bitfield deasserts ('0') after deasserting db0_fsm_reset.
2..0 | Reserved

### Offset 0x13000: RF_AXI_STATUS_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
RF_AXI_STATUS_REG
offset=0x13000
Total Offset =
0x1000153000

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.
It uses RegType RF_AXI_STATUS_REGTYPE which is defined in HDL source file common_regs.v.

Status register for the RF AXI-Stream interfaces.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.

Bits | Name
31..30 | USER_ADC_TREADY_DB1 This bitfield is wired to the user's ADC (DB1) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1.
29..28 | USER_ADC_TVALID_DB1 This bitfield is wired to the user's ADC (DB1) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1.
27..26 | RFDC_ADC_I_TVALID_DB1 This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TValid handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1.
25..24 | RFDC_ADC_Q_TVALID_DB1 This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TValid handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1.
23..22 | RFDC_ADC_I_TREADY_DB1 This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TReady handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1.
21..20 | RFDC_ADC_Q_TREADY_DB1 This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TReady handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1.
19..18 | RFDC_DAC_TVALID_DB1 This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1.
17..16 | RFDC_DAC_TREADY_DB1 This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1.
15..14 | USER_ADC_TREADY This bitfield is wired to the user's ADC (DB0) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1.
13..12 | USER_ADC_TVALID This bitfield is wired to the user's ADC (DB0) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1.
11..10 | RFDC_ADC_I_TVALID This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TValid handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1.
9..8 | RFDC_ADC_Q_TVALID This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TValid handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1.
7..6 | RFDC_ADC_I_TREADY This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TReady handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1.
5..4 | RFDC_ADC_Q_TREADY This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TReady handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1.
3..2 | RFDC_DAC_TVALID This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1.
1..0 | RFDC_DAC_TREADY This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1.

### Offset 0x13008: FABRIC_DSP_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
FABRIC_DSP_REG
offset=0x13008
Total Offset =
0x1000153008

Initial Value = 0x00000000

This register is defined in HDL source file x410_rfdc_regs.v.
It uses RegType FABRIC_DSP_REGTYPE which is defined in HDL source file common_regs.v.

This register provides information to the driver on the type of DSP that is instantiated in the fabric.
The X410 platform supports multiple RF daughterboards, each requiring a different fabric RF DSP chain that works with specific RFDC settings. Each bandwidth DSP chain has a unique identifier (BW in MHz), this information is conveyed in this register to let the driver configure the RFDC with the proper settings. Also, channel count for the DSP module is included.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.

Bits | Name
31..20 | FABRIC_DSP_BW (initialvalue=FABRIC_DSP_BW_NONE) Fabric DSP BW in MHz for both daughterboards. The values for this bitfield are in the FABRIC_DSP_BW_ENUM table. (show here)
Value | Name
Dec | Hex
0 | 0x000 | FABRIC_DSP_BW_NONE
100 | 0x064 | FABRIC_DSP_BW_100M
200 | 0x0C8 | FABRIC_DSP_BW_200M
400 | 0x190 | FABRIC_DSP_BW_400M
1000 | 0x3E8 | FABRIC_DSP_BW_FULL
This enumerated type is defined in HDL source file common_regs.v.
19..18 | FABRIC_DSP_RESERVED_DB1 (initialvalue=0) Reserved for future use.
17..14 | FABRIC_DSP_TX_CNT_DB1 (initialvalue=0) Fabric DSP TX channel count for daughterboard 0.
13..10 | FABRIC_DSP_RX_CNT_DB1 (initialvalue=0) Fabric DSP RX channel count for daughterboard 0.
9..8 | FABRIC_DSP_RESERVED (initialvalue=0) Reserved for future use.
7..4 | FABRIC_DSP_TX_CNT (initialvalue=0) Fabric DSP TX channel count for daughterboard 0.
3..0 | FABRIC_DSP_RX_CNT (initialvalue=0) Fabric DSP RX channel count for daughterboard 0.

### Offset 0x14000: CALIBRATION_DATA Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
CALIBRATION_DATA
offset=0x14000
Total Offset =
0x1000154000

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

The fields of this register provide data to all the DAC channels when enabled by the CALIBRATION_ENABLE register.

Bits | Name
31..16 | Q_DATA
15..0 | I_DATA

### Offset 0x14008: CALIBRATION_ENABLE Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
CALIBRATION_ENABLE
offset=0x14008
Total Offset =
0x1000154008

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

This register enables calibration data in the DAC data path for each of the four channels. Each of these bits is normally '0'. When written '1', DAC data for the corresponding channel will be constantly driven with the contents of the CALIBRATION_DATA register.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..6 | Reserved
5 | ENABLE_CALIBRATION_DATA_3 Enables calibration data for channel 3.
4 | ENABLE_CALIBRATION_DATA_2 Enables calibration data for channel 2.
3..2 | Reserved
1 | ENABLE_CALIBRATION_DATA_1 Enables calibration data for channel 1.
0 | ENABLE_CALIBRATION_DATA_0 Enables calibration data for channel 0.

### Offset 0x15000: THRESHOLD_STATUS Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
THRESHOLD_STATUS
offset=0x15000
Total Offset =
0x1000155000

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

This register shows threshold status for the ADCs. Each bit reflects the RFDC's real-time ADC status signals, which will assert when the ADC input signal exceeds the programmed threshold value. The status will remain asserted until cleared by software. The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is the location of the tile in the converter column and ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). See also the Xilinx document PG269.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | Reserved
11 | ADC2_23_THRESHOLD2
10 | ADC2_23_THRESHOLD1
9 | ADC2_01_THRESHOLD2
8 | ADC2_01_THRESHOLD1
7..4 | Reserved
3 | ADC0_23_THRESHOLD2
2 | ADC0_23_THRESHOLD1
1 | ADC0_01_THRESHOLD2
0 | ADC0_01_THRESHOLD1

### Offset 0x16000: RF_PLL_CONTROL_REG Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
RF_PLL_CONTROL_REG
offset=0x16000
Total Offset =
0x1000156000

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

Enable RF MMCM outputs.

Bits | Name
31..24 | Reserved
23..17 | Reserved
16 | CLEAR_DATA_CLK_UNLOCKED
15..13 | Reserved
12 | ENABLE_RF_CLK_2X
11..9 | Reserved
8 | ENABLE_RF_CLK
7..5 | Reserved
4 | ENABLE_DATA_CLK_2X
3..1 | Reserved
0 | ENABLE_DATA_CLK

### Offset 0x16008: RF_PLL_STATUS_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
RF_PLL_STATUS_REG
offset=0x16008
Total Offset =
0x1000156008

Initial Value not specified

This register is defined in HDL source file x410_rfdc_regs.v.

Data Clk Pll Status Register

Bits | Name
31..24 | Reserved
23..21 | Reserved
20 | DATA_CLK_PLL_LOCKED
19..17 | Reserved
16 | DATA_CLK_PLL_UNLOCKED_STICKY
15..8 | Reserved
7..0 | Reserved

### Offset 0x17000: ADC_TILEMAP_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
ADC_TILEMAP_REG
offset=0x17000
Total Offset =
0x1000157000

Initial Value = 0x00000000

This register is defined in HDL source file x410_rfdc_regs.v.
It uses RegType ADC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.

This register describes how the ADCs map to the respective tiles. It lets us designate an ADC as channel 0, channel 1, etc. depending on how those channels are externally connected to the RFSoC.
For every channel, this register stores the tile number and the block number of the converter. This can be used to then address the correct converter in the various Xilinx interfaces/APIs.

Bits | Name
31..30 | ADC_TILEMAP_DB1_CHAN3_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 3, daughterboard 1.
29..28 | ADC_TILEMAP_DB1_CHAN3_TILE (initialvalue=0) Tile number of the ADC for channel 3, daughterboard 1.
27..26 | ADC_TILEMAP_DB1_CHAN2_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 2, daughterboard 1.
25..24 | ADC_TILEMAP_DB1_CHAN2_TILE (initialvalue=0) Tile number of the ADC for channel 2, daughterboard 1.
23..22 | ADC_TILEMAP_DB1_CHAN1_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 1, daughterboard 1.
21..20 | ADC_TILEMAP_DB1_CHAN1_TILE (initialvalue=0) Tile number of the ADC for channel 1, daughterboard 1.
19..18 | ADC_TILEMAP_DB1_CHAN0_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 0, daughterboard 1.
17..16 | ADC_TILEMAP_DB1_CHAN0_TILE (initialvalue=0) Tile number of the ADC for channel 0, daughterboard 1.
15..14 | ADC_TILEMAP_DB0_CHAN3_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 3, daughterboard 0.
13..12 | ADC_TILEMAP_DB0_CHAN3_TILE (initialvalue=0) Tile number of the ADC for channel 3, daughterboard 0.
11..10 | ADC_TILEMAP_DB0_CHAN2_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 2, daughterboard 0.
9..8 | ADC_TILEMAP_DB0_CHAN2_TILE (initialvalue=0) Tile number of the ADC for channel 2, daughterboard 0.
7..6 | ADC_TILEMAP_DB0_CHAN1_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 1, daughterboard 0.
5..4 | ADC_TILEMAP_DB0_CHAN1_TILE (initialvalue=0) Tile number of the ADC for channel 1, daughterboard 0.
3..2 | ADC_TILEMAP_DB0_CHAN0_BLOCK (initialvalue=0) Block number (within the tile) of the ADC for channel 0, daughterboard 0.
1..0 | ADC_TILEMAP_DB0_CHAN0_TILE (initialvalue=0) Tile number of the ADC for channel 0, daughterboard 0.

### Offset 0x17008: DAC_TILEMAP_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
DAC_TILEMAP_REG
offset=0x17008
Total Offset =
0x1000157008

Initial Value = 0x00000000

This register is defined in HDL source file x410_rfdc_regs.v.
It uses RegType DAC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.

This register describes how the DACs map to the respective tiles. It lets us designate an DAC as channel 0, channel 1, etc. depending on how those channels are externally connected to the RFSoC.
For every channel, this register stores the tile number and the block number of the converter. This can be used to then address the correct converter in the various Xilinx interfaces/APIs.

Bits | Name
31..30 | DAC_TILEMAP_DB1_CHAN3_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 3, daughterboard 1.
29..28 | DAC_TILEMAP_DB1_CHAN3_TILE (initialvalue=0) Tile number of the DAC for channel 3, daughterboard 1.
27..26 | DAC_TILEMAP_DB1_CHAN2_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 2, daughterboard 1.
25..24 | DAC_TILEMAP_DB1_CHAN2_TILE (initialvalue=0) Tile number of the DAC for channel 2, daughterboard 1.
23..22 | DAC_TILEMAP_DB1_CHAN1_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 1, daughterboard 1.
21..20 | DAC_TILEMAP_DB1_CHAN1_TILE (initialvalue=0) Tile number of the DAC for channel 1, daughterboard 1.
19..18 | DAC_TILEMAP_DB1_CHAN0_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 0, daughterboard 1.
17..16 | DAC_TILEMAP_DB1_CHAN0_TILE (initialvalue=0) Tile number of the DAC for channel 0, daughterboard 1.
15..14 | DAC_TILEMAP_DB0_CHAN3_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 3, daughterboard 0.
13..12 | DAC_TILEMAP_DB0_CHAN3_TILE (initialvalue=0) Tile number of the DAC for channel 3, daughterboard 0.
11..10 | DAC_TILEMAP_DB0_CHAN2_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 2, daughterboard 0.
9..8 | DAC_TILEMAP_DB0_CHAN2_TILE (initialvalue=0) Tile number of the DAC for channel 2, daughterboard 0.
7..6 | DAC_TILEMAP_DB0_CHAN1_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 1, daughterboard 0.
5..4 | DAC_TILEMAP_DB0_CHAN1_TILE (initialvalue=0) Tile number of the DAC for channel 1, daughterboard 0.
3..2 | DAC_TILEMAP_DB0_CHAN0_BLOCK (initialvalue=0) Block number (within the tile) of the DAC for channel 0, daughterboard 0.
1..0 | DAC_TILEMAP_DB0_CHAN0_TILE (initialvalue=0) Tile number of the DAC for channel 0, daughterboard 0.

### Offset 0x18000: RFDC_INFO_REG Register (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|RFDC_REGS
0x1000140000
RFDC_INFO_REG
offset=0x18000
Total Offset =
0x1000158000

Initial Value = 0x00910091

This register is defined in HDL source file x410_rfdc_regs.v.
It uses RegType RFDC_INFO_REGTYPE which is defined in HDL source file common_regs.v.

This register provides information about how the RFDC is connected to the rest of the fabric.
Specifically, between the actual RFDC and the RFNoC infrastructure, there may be additional resampling (if the RFDC resampler cannot handle all the resampling itself) and it is important to know how wide the connection from the RFDC gearbox FIFO to the rest of the design is. Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.

Bits | Name
31..26 | Reserved
25..23 | RFDC_INFO_SPC_TX_DB1 (initialvalue=1) Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.
22..20 | RFDC_INFO_SPC_RX_DB1 (initialvalue=1) Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.
19..16 | RFDC_INFO_XTRA_RESAMP_DB1 (initialvalue=1) Additional resampling happening outside the RFDC for daughterboard 0.
15..10 | Reserved
9..7 | RFDC_INFO_SPC_TX (initialvalue=1) Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.
6..4 | RFDC_INFO_SPC_RX (initialvalue=1) Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.
3..0 | RFDC_INFO_XTRA_RESAMP (initialvalue=1) Additional resampling happening outside the RFDC for daughterboard 0.

# RFDC_TIMING_REGMAP

## RFDC_TIMING_REGS

### Offset 0x0000: NCO_RESET_REG Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW
0x008000
NCO_RESET_REG
offset=0x0000
Total Offset =
0x008000

Initial Value not specified

This register is defined in HDL source file rfdc_timing_control.v.

NCO reset control register.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..2 | Reserved
1r | NCO_RESET_DONE When 1, indicates that the NCO reset has completed.
0w | NCO_RESET_START (Strobe) Write a 1 to this bit to start a reset the RFDC's NCO.

### Offset 0x0004: GEARBOX_RESET_REG Register (R|W)

(show extended info)

RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW
0x008000
GEARBOX_RESET_REG
offset=0x0004
Total Offset =
0x008004

Initial Value not specified

This register is defined in HDL source file rfdc_timing_control.v.

Gearbox reset control register.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..2 | Reserved
1w | DAC_RESET (Strobe) This reset is for the gearbox on the DAC data path that is used to move data from one clock domain to another outside the RFDC. Write a 1 to this bit to send a reset pulse to the DAC gearbox.
0w | ADC_RESET (Strobe) This reset is for the gearbox on the ADC data path that is used to move data from one clock domain to another outside the RFDC. Write a 1 to this bit to send a reset pulse to the ADC gearbox.

# SPI_REGMAP

## SPI_REGS

This register map is present for each SPI master.

For information about the register content and the way to interact with the core see the documentation of the SPI master from opencores used internally.

The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider. Only 64 bits of data are available via this register interface.

For the different SPI modes use the following table to derive the bits in CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.

CPOL | CPHA | TX_NEG | RX_NEG
--- | --- | --- | ---
0 | 0 | 1 | 0
0 | 1 | 0 | 1
1 | 0 | 0 | 1
1 | 1 | 1 | 0

### Offset 0x0000: RX_DATA_LOW Register (R)

(show extended info)

RX_DATA_LOW
offset=0x0000

Initial Value not specified

This register is defined in HDL source file ctrlport_to_spi.v.

Lower 32 bits of the received word. (RxWord[31:0])

### Offset 0x0004: RX_DATA_HIGH Register (R)

(show extended info)

RX_DATA_HIGH
offset=0x0004

Initial Value not specified

This register is defined in HDL source file ctrlport_to_spi.v.

Higher 32 bits of the received word. (RxWord[63:32])

### Offset 0x0008: TX_DATA_LOW Register (W)

(show extended info)

TX_DATA_LOW
offset=0x0008

Initial Value not specified

This register is defined in HDL source file ctrlport_to_spi.v.

Lower 32 bits of the received word. (TxWord[31:0])

### Offset 0x000C: TX_DATA_HIGH Register (W)

(show extended info)

TX_DATA_HIGH
offset=0x000C

Initial Value not specified

This register is defined in HDL source file ctrlport_to_spi.v.

Higher 32 bits of the received word. (TxWord[63:32])

### Offset 0x0010: CONTROL Register (R|W)

(show extended info)

CONTROL
offset=0x0010

Initial Value not specified

This register is defined in HDL source file ctrlport_to_spi.v.

Control register

### Offset 0x0014: CLOCK_DIVIDER Register (R|W)

(show extended info)

CLOCK_DIVIDER
offset=0x0014

Initial Value not specified

This register is defined in HDL source file ctrlport_to_spi.v.

Bits | Name
7..0 | Divider Clock Divider.

### Offset 0x0018: SLAVE_SELECT Register (R|W)

(show extended info)

SLAVE_SELECT
offset=0x0018

Initial Value not specified

This register is defined in HDL source file ctrlport_to_spi.v.

Bits | Name
15..0 | SS Slave select.

# UIO_REGMAP

## UIO_REGS

UIO

### Offset 0x0000: IP Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
IP
offset=0x0000
Total Offset =
0x120000A000
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A000
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A000
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A000
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A000
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A000
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A000
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A000

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Set this port's IP address

### Offset 0x0004: UDP Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
UDP
offset=0x0004
Total Offset =
0x120000A004
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A004
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A004
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A004
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A004
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A004
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A004
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A004

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Set the UDP port for CHDR_traffic

### Offset 0x0010: BRIDGE_MAC_LSB Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
BRIDGE_MAC_LSB
offset=0x0010
Total Offset =
0x120000A010
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A010
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A010
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A010
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A010
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A010
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A010
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A010

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

If BRIDGE_ENABLE is set use this MAC_ID

### Offset 0x0014: BRIDGE_MAC_MSB Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
BRIDGE_MAC_MSB
offset=0x0014
Total Offset =
0x120000A014
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A014
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A014
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A014
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A014
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A014
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A014
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A014

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

If BRIDGE_ENABLE is set use this MAC_ID

### Offset 0x0018: BRIDGE_IP Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
BRIDGE_IP
offset=0x0018
Total Offset =
0x120000A018
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A018
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A018
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A018
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A018
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A018
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A018
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A018

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

If BRIDGE_ENABLE is set use this IP Address

### Offset 0x001C: BRIDGE_UDP Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
BRIDGE_UDP
offset=0x001C
Total Offset =
0x120000A01C
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A01C
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A01C
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A01C
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A01C
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A01C
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A01C
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A01C

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic

### Offset 0x0020: BRIDGE_ENABLE Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
BRIDGE_ENABLE
offset=0x0020
Total Offset =
0x120000A020
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A020
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A020
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A020
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A020
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A020
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A020
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A020

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Bit 0 Controls the following logic

    always_comb begin : bridge_mux
    my_mac            = bridge_en ? bridge_mac_reg : mac_reg;
    my_ip             = bridge_en ? bridge_ip_reg : ip_reg;
    my_udp_chdr_port  = bridge_en ? bridge_udp_port : udp_port;
    end

### Offset 0x0030: CHDR_DROPPED Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
CHDR_DROPPED
offset=0x0030
Total Offset =
0x120000A030
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A030
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A030
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A030
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A030
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A030
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A030
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A030

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Count the number of Packets dropped that were addressed to the CHDR section.

### Offset 0x0034: CPU_DROPPED Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
CPU_DROPPED
offset=0x0034
Total Offset =
0x120000A034
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A034
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A034
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A034
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A034
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A034
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A034
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A034

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Count the number of Packets dropped that were addressed to us, but not to the CHDR section.

### Offset 0x0038: PAUSE Register (R|W)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|QSFP_0_0
0x1200000000
QSFP_REGMAP|UIO
0x00A000
PAUSE
offset=0x0038
Total Offset =
0x120000A038
AXI_HPM0_REGMAP|QSFP_0_1
0x1200010000
Total Offset =
0x120001A038
AXI_HPM0_REGMAP|QSFP_0_2
0x1200020000
Total Offset =
0x120002A038
AXI_HPM0_REGMAP|QSFP_0_3
0x1200030000
Total Offset =
0x120003A038
AXI_HPM0_REGMAP|QSFP_1_0
0x1200040000
Total Offset =
0x120004A038
AXI_HPM0_REGMAP|QSFP_1_1
0x1200050000
Total Offset =
0x120005A038
AXI_HPM0_REGMAP|QSFP_1_2
0x1200060000
Total Offset =
0x120006A038
AXI_HPM0_REGMAP|QSFP_1_3
0x1200070000
Total Offset =
0x120007A038

Initial Value not specified

This register is defined in HDL source file uhd_regs.v.

Bits | Name
31..16 | pause_clear If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause. Pause clear must be less than pause set or terrible things will happen. The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only used with 100Gb ethernet
15..0 | pause_set If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only used with 100Gb ethernet

# VERSIONING_REGS_REGMAP

## VERSIONING_CONSTANTS

### CPLD_IFC_VERSION Enumeration

CPLD interface module.
For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
- Current version: CURRENT_VERSION
- Oldest compatible version: OLDEST_COMPATIBLE_VERSION
- Version last modified: VERSION_LAST_MODIFIED

  Value | Name
  Dec | Hex
  0 | 0x00000000 | CPLD_IFC_CURRENT_VERSION_MINOR
  0 | 0x00000000 | CPLD_IFC_CURRENT_VERSION_BUILD
  0 | 0x00000000 | CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
  0 | 0x00000000 | CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
  2 | 0x00000002 | CPLD_IFC_CURRENT_VERSION_MAJOR
  2 | 0x00000002 | CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
  553719817 | 0x21011809 | CPLD_IFC_VERSION_LAST_MODIFIED_TIME

  This enumerated type is defined in HDL source file cpld_interface_regs.v.

### DB_GPIO_IFC_VERSION Enumeration

Daughterboard GPIO interface.
For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
- Current version: CURRENT_VERSION
- Oldest compatible version: OLDEST_COMPATIBLE_VERSION
- Version last modified: VERSION_LAST_MODIFIED

  Value | Name
  Dec | Hex
  0 | 0x00000000 | DB_GPIO_IFC_CURRENT_VERSION_MINOR
  0 | 0x00000000 | DB_GPIO_IFC_CURRENT_VERSION_BUILD
  0 | 0x00000000 | DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
  0 | 0x00000000 | DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
  1 | 0x00000001 | DB_GPIO_IFC_CURRENT_VERSION_MAJOR
  1 | 0x00000001 | DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
  537986582 | 0x20110616 | DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME

  This enumerated type is defined in HDL source file db_gpio_interface.v.

### FPGA_VERSION Enumeration

FPGA version.
For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
- Current version: CURRENT_VERSION
- Oldest compatible version: OLDEST_COMPATIBLE_VERSION
- Version last modified: VERSION_LAST_MODIFIED

  Value | Name
  Dec | Hex
  0 | 0x00000000 | FPGA_CURRENT_VERSION_MINOR
  0 | 0x00000000 | FPGA_CURRENT_VERSION_BUILD
  0 | 0x00000000 | FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
  0 | 0x00000000 | FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
  8 | 0x00000008 | FPGA_CURRENT_VERSION_MAJOR
  8 | 0x00000008 | FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
  587472913 | 0x23042011 | FPGA_VERSION_LAST_MODIFIED_TIME

  This enumerated type is defined in HDL source file x4xx.v.

### RF_CORE_100M_VERSION Enumeration

100 MHz RF core.
For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
- Current version: CURRENT_VERSION
- Oldest compatible version: OLDEST_COMPATIBLE_VERSION
- Version last modified: VERSION_LAST_MODIFIED

  Value | Name
  Dec | Hex
  0 | 0x00000000 | RF_CORE_100M_CURRENT_VERSION_MINOR
  0 | 0x00000000 | RF_CORE_100M_CURRENT_VERSION_BUILD
  0 | 0x00000000 | RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR
  0 | 0x00000000 | RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD
  1 | 0x00000001 | RF_CORE_100M_CURRENT_VERSION_MAJOR
  1 | 0x00000001 | RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR
  537929239 | 0x20102617 | RF_CORE_100M_VERSION_LAST_MODIFIED_TIME

  This enumerated type is defined in HDL source file rf_core_100m.v.

### RF_CORE_400M_VERSION Enumeration

400 MHz RF core.
For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
- Current version: CURRENT_VERSION
- Oldest compatible version: OLDEST_COMPATIBLE_VERSION
- Version last modified: VERSION_LAST_MODIFIED

  Value | Name
  Dec | Hex
  0 | 0x00000000 | RF_CORE_400M_CURRENT_VERSION_MINOR
  0 | 0x00000000 | RF_CORE_400M_CURRENT_VERSION_BUILD
  0 | 0x00000000 | RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR
  0 | 0x00000000 | RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD
  1 | 0x00000001 | RF_CORE_400M_CURRENT_VERSION_MAJOR
  1 | 0x00000001 | RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR
  537929239 | 0x20102617 | RF_CORE_400M_VERSION_LAST_MODIFIED_TIME

  This enumerated type is defined in HDL source file rf_core_400m.v.

## VERSIONING_REGS

### COMPONENTS_INDEXES Enumeration

This enum contains indexes for all the components in the X410 (both common and app-specific) which version information is desired to be available for compatibility tracking purposes.

Description | Index range | Max # of components
--- | --- | ---
Common components | 0 to 23 | 24
UHD-specific components | 24 to 43 | 20
LV-specific components | 44 to 63 | 20

Value | Name
0 | FPGA_VERSION_INDEX
1 | CPLD_IFC_INDEX
2 | DB0_RF_CORE_INDEX
3 | DB1_RF_CORE_INDEX
4 | DB0_GPIO_IFC_INDEX
5 | DB1_GPIO_IFC_INDEX

This enumerated type is defined in HDL source file x4xx_versioning_regs.v.

### Offset 0x0000: CURRENT_VERSION(63:0) Register Array (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|VERSIONING_REGS
0x000C00
CURRENT_VERSION
offset=0x0000 + i*0x10
Cannot determine accessibility through this path
Total Offset =
0x10000A0C00 + i*0x10

Initial Values

default | => | 0x00000000

This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

Component's current version.
This register contains the current component's version implemented in HDL. The current version shall be used to detect a component being too old for the driver/software:
SW oldest compatible version > Component's current version --> Component is too old.

Bits | Name
31..23 | MAJOR (initialvalue=0) Major number (max = 511): an increase reflects a breaking change. IMPORTANT! MAJOR must always remain in sync between the component's CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers. Update MAJOR when: the component has changed and requires a software changes as a result. the component's bitfields/registers have been modified or deleted. the component's bitfields/registers are initialized to different value (unexpected by software). new bitfields/registers are added that require software interaction for the component to operate.
22..12 | MINOR (initialvalue=0) Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of. Update MINOR when: a new feature is added to the component, which does not conflict with the driver. minor implementation changes were made to the component which are worth tracking. the component has added new bitfields/registers that do not require software interaction (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to previously undefined bits). MAJOR is updated (reset MINOR to 0).
11..0 | BUILD (initialvalue=0) Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation, but that should not impact the component's behavior Eventually, this number is intended to be automatically incremented for any new build. Meanwhile, update BUILD when: the component's source code changes are not captured by MAJOR or MINOR. MINOR or MAJOR are updated (reset BUILD to 0).

### Offset 0x0004: OLDEST_COMPATIBLE_VERSION(63:0) Register Array (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|VERSIONING_REGS
0x000C00
OLDEST_COMPATIBLE_VERSION
offset=0x0004 + i*0x10
Cannot determine accessibility through this path
Total Offset =
0x10000A0C04 + i*0x10

Initial Values

default | => | 0x00000000

This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

Component's oldest compatible version.
This register contains the oldest compatible component's version, that is the oldest component's implementation that is compatible with the current implementation.
The oldest compatible version shall be used to detect a component being too new for the driver/software:
SW current version < Component's oldest compatible version --> Component is too new.

Bits | Name
31..23 | MAJOR (initialvalue=0) Major number (max = 511): an increase reflects a breaking change. IMPORTANT! MAJOR must always remain in sync between the component's CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers. Update MAJOR when: the component has changed and requires a software changes as a result. the component's bitfields/registers have been modified or deleted. the component's bitfields/registers are initialized to different value (unexpected by software). new bitfields/registers are added that require software interaction for the component to operate.
22..12 | MINOR (initialvalue=0) Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of. Update MINOR when: a new feature is added to the component, which does not conflict with the driver. minor implementation changes were made to the component which are worth tracking. the component has added new bitfields/registers that do not require software interaction (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to previously undefined bits). MAJOR is updated (reset MINOR to 0).
11..0 | BUILD (initialvalue=0) Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation, but that should not impact the component's behavior Eventually, this number is intended to be automatically incremented for any new build. Meanwhile, update BUILD when: the component's source code changes are not captured by MAJOR or MINOR. MINOR or MAJOR are updated (reset BUILD to 0).

### Offset 0x0008: VERSION_LAST_MODIFIED(63:0) Register Array (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|VERSIONING_REGS
0x000C00
VERSION_LAST_MODIFIED
offset=0x0008 + i*0x10
Cannot determine accessibility through this path
Total Offset =
0x10000A0C08 + i*0x10

Initial Value not specified

This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType TIMESTAMP_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

Component's versions update time.
This register provides the time stamp for the last modification to the component's versions (current & oldest compatible). The time stamp is provided in hexadecimal format: 0xYYMMDDHH.

Bits | Name
31..24 | YY This is the year number after 2000 (e.g. 2019 = 0x19).
23..16 | MM
15..8 | DD
7..0 | HH

### Offset 0x000C: RESERVED(63:0) Register Array (R)

(show extended info)

Port ARM_M_AXI_HPM0
AXI_HPM0_REGMAP|CORE_REGS
0x10000A0000
CORE_REGS_REGMAP|VERSIONING_REGS
0x000C00
RESERVED
offset=0x000C + i*0x10
Cannot determine accessibility through this path
Total Offset =
0x10000A0C0C + i*0x10

Initial Value not specified

This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType RESERVED_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

Reserved.

# XGE_MAC_REGMAP

## OPENCORE_XGE_REGISTERS

10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf